Configuring Spike to model your RISC-V implementation

RISC-V International implemented and maintains “Spike”, an Instruction Set Simulator for RISC-V written in C++. Spike is often referred to as the “golden reference model” for RISC-V, although RISC-V International makes no such claim. Nevertheless, because it has been in wide-spread use for more than a decade and its GitHub repository is still active, it is considered a very high fidelity model, and it is often used as a Reference Model for other implementations. It is not always appreciated by users of Spike that it is a model of a specific implementation, and many of the design decisions made for Spike may not match the design decisions made for your specific implementation. Worse, these design decisions are not well documented and are often hidden in the C++ model itself. This paper details how OpenHW has approached the problem of first identifying Spike implementation decisions and then configuring Spike to match the implementation decisions of OpenHW cores, specfically the CV32A60X and the CV32E20.

Mike is a functional verification engineer and manager who has been involved in all aspects of the discipline: simulation, emulation, prototyping and formal verification. He is strong proponent of coverage driven processes in the pursuit of first-time-right silicon.