Verification Futures » VF2025 UK

Verification Futures Conference 2025 UK

The Verification Futures conference has always provided a unique blend of conference presentations, exhibitions, training and industry networking sessions for discussing the challenges faced in hardware and software verification thus providing a unique opportunity for end-users to define their verification challenges and collaborate with the other engineers and vendors to create solutions. In 2025 Verification Futures UK is expanding to include the use of AI/ML in IP/SoC, FPGA and Mixed Signal designs, as well as new tracks for UK Engineering students and UK-based semiconductor start-ups.

Event at a Glance

Tuesday, 01 July 2025 – Full day conference, exhibition and networking event

Reading (UK) & online

FREE to attend conference In-Person or Online

Presentation guidelines for speakers

Conference Program

08:30

Exhibition open and student posters available for viewing

09:25

Conference starts

09:30

The four horse riders of the silicon apocalypse

Sean Redmond (Silicon Catalyst UK)

10:00

Conference Sponsor - Platinum Plus - Cadence

10:30

Break - Exhibition open and student posters available for viewing

	Verification
	Main Morning	TBC (Breakout)	Training Engineers in work	Mixed Signal	UKESF	Design	FPGA Verification
11:00	Main Morning Synopsys – Platinum Sponsor	Speaker	Doulos Training (topic TBD)	Mixed Signal Platinum Design? Sponsor speaker?	UK ESF Stream for invited students	AI/ML in Design Flows Platinum Design Sponsor speaker	FPGA Test Benches Platinum Design Sponsor speaker
11:30	VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL Anna Duque Antón (RPTU Kaiserslautern-Landau)	Speaker		Speaker		Speaker	Speaker
11:50	A novel formal verification solution to Non-convergence Surinder Sood (ARM)	Speaker		Speaker		Speaker	Speaker
12:10	Speaker	Speaker		Speaker		Speaker	Speaker

12:30

Lunch - Exhibition open and student posters available for viewing

13:30	Afternoon Verification Session	Mixed Signal	UKESF	AI Design IP	Verifying IP designs in FPGA
13:30	Platinum Verif Sponsor Speaker Siemens – Platinum Sponsor	Platinum Sponsor Speaker	UK ESF Stream for invited students	Platinum Design IP Sponsor Speaker	Platinum FPGA Sponsor Speaker CocoTB
14:00	Bringing CI into Formal Verification Tobias Ludwig (LUBIS EDA)	Speaker		Mrudula Gore Imgtec	CocoTB
14:20	Gold Sponsor Speaker	Speaker		Speaker	HDLRegression: A reliable and efficient tool for FPGA regression testing Marius Elvegård (Inventas)
14:40	Gold Sponsor Speaker	Speaker		Speaker	Speaker

15:00

Break - Exhibition open and student posters available for viewing

	Advance Verification Topics
15.30	Main Afternoon	CPU/RISCV Verification (Breakout)	AI in DV	Mixed Signal	UKESF	Design	FPGA
15:30	Multisim: simulate your RTL with real multi-threaded speed Antoine Madec (Axelera AI)	Configuring Spike to model your RISC-V implementation Mike Thompson (OpenHW Founation)	Kerstin Eder – Bristol University	Speaker	UK ESF Stream for invited students	AI IP in SoC Martin Zeller, Dreamchip	top-level verif for FPGA with AI Speaker
15:50	Mrudula Gore Imgtec (colleague)	Formal Verification of Security-Properties on RISC-V Processors Christian Appold (Denso Automotive Deutschland GmbH)		Speaker		Gareth Richard, TechWorks	Speaker
16:10	AFCML: Accelerating the Functional Coverage through Machine Learning within a UVM Framework Haroon Waris (Institute of Space Technology (IST))	𝜇CFI: Formal Verification of Microarchitectural Control-flow Integrity Katharina Ceesay-Seitz (ETH Zurich)		Speaker		Testing and verifying the tools of hardware design John Wickerson(Imperial College London))	Speaker

16:30

Drinks and Pizza, student poster competition prize giving, sponsor gift raffle draw

17:00

End of conference

Sponsors

VF2025 was made possible through the generosity of the following sponsors. If you would like to become a VF2025 sponsor please Contact Us.