Randomisation in the Real world

Constrained-random verification (CRV) is a well-established and successful methodology for digital designs and UVM has become the primary means to achieve this. The functional complexity in mixed-signal designs is increasing exponentially. Even a simple Power Management Unit can have hundreds or thousands of control bits and many modes of operation. To achieve good functional coverage it is important to adopt a CRV approach for mixed-signal designs. This approach can help us manage a large verification space, including: checking analogue performance under a large set of programmable configurations; digital control system interaction with analogue circuits; covering unexpected corner cases in A/D interaction. This presentation shows some of the ways in which Renesas has applied UVM to mixed-signal designs and some of the benefits we gained by doing so.

Steve has 24 years experience of digital verification including eRM, OVM, UVM and formal property checking. He has led the verification of large scale consumer SoC projects. He joined Dialog Semiconductor in 2011 and previously worked for Doulos, NXP and Trident Microsystems. He is an active member of the Accellera UVM-Mixed Signal Working Group.