Is it easy to get started with UVM, or should I use Formal instead?

The Universal Verification Methodology (UVM) is an IEEE standard which provides a library of base classes, a framework and rules that enable complex simulation environments to be created in SystemVerilog. Unfortunately, beginners often struggle to understand the multitude of features provided by UVM. This presentation will introduce a subset of UVM, that makes it easier to get started and will show how these can be used to create a simple UVM testbench. However, a simulation-based approach is not always the best way to verify a design: Formal verification is also possible in SystemVerilog. The presentation will conclude with an overview of formal verification in SystemVerilog and consider how to decide the most appropriate approach to take.

Matthew Taylor has been a key member of the Doulos technical team since 2014, specialising in Hardware Description Language-based design and verification, formal verification, and digital hardware design. As well as developing, writing, and presenting training courses, Matthew is responsible for the day-to-day running and the development of the EDA Playground website, which is owned by Doulos. He is also an Employee Trustee of Doulos, which is an employee-owned company.

Matthew has an MEng in Electrical and Electronic Engineering and holds patents for 25 inventions in digital TV demodulation across 40 countries and regions. Before joining Doulos, Matthew worked at Sony for 16 years where he designed and managed the development of ICs (for digital TV and mobile phones) and designed algorithms for digital TV demodulation. Before that he worked at Siemens (Roke Manor) where he designed FPGA/ICs and embedded software for various radio systems. In total, he has 35 years’ experience of electronics design and verification.