Autonomous Verification – Are We There Yet?

We are now in the era of pervasive intelligence from voice assistants, advanced robotics, drone-based delivery to autonomous cars and chatbots. This begs the question, how are we doing in design verification? Design verification is one of the most expensive and time-consuming activities for any chip design. Moreover, every year the cost of design verification grows exponentially and despite that ½ of design re-spins are caused by functional or logic bugs. When we consider where time is spent in verification, coverage convergence and debug consume 70% of overall verification time. In addition to time spent, misinterpretation of specifications is a major source of bugs. With the rapid evolution of AI/ML technologies, how can we automate some or many of these activities? What technologies are available today and what is on the horizon? With the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models, what are the possibilities in design verification? Just like there are 6 levels of driving automation, from driver assistance to conditional automation to full automation, what level is the current state of verification? This presentation will explore these topics and look ahead to the future of autonomous verification.

Bradley Geden is the Senior Director of product management for verification software at Synopsys. He has over 20 years of experience in the EDA industry covering a broad range of domains such as custom design, circuit simulation, digital implementation and verification in both product management and sales roles at Synopsys and Siemens EDA. Prior to entering the world of EDA he was an analog mixed-signal design engineer working on energy measurement and wireless communication chips. In his spare time, Bradley enjoys travelling and exploring the world with his wife, preferably on a sailboat!