Tessolve, a worldwide provider of engineering solutions spanning complex chip design, semiconductor hardware and software development, testing, failure analysis, and embedded systems development is happy to announce that the Verification Futures Conference. The conference, which is entering its 11th successful year in the UK, is coming to Austin (USA) for the first time on Thursday, September 14, 2023, with both physical and virtual access (register here). The conference is focused on hardware design verification.
The full conference program includes 17 talks covering verification challenges and solutions, formal verification, RISC-V, System Verilog, UVM for AMS Verification, and VHDL Verification. The complete conference agenda can be viewed below with links to details on the talks. Register now to become a part of this event in-person or online. Click here to register.
The event is free to attend, thanks to our generous sponsors Cadence, Imperas, Breker Systems, and Doulos.
Below is the full conference program
Click here to watch the video!
| 08:30 | Arrival: Breakfast and Networking | |||
| 09:25 | Welcome: Mike Bartley, Tessolve Semiconductor Ltd | |||
| 09:30 | Safety and Security challenges in hardware IP development Vivek Vedula, ARM Ltd (45 minutes) |
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| 10:15 | User Top Verification Challenges | |||
| 10:15 | Ericsson’s Challenges of IP Development and Verification for Products with a Long Shelf Life Alex Duhovich, Ericsson (15 Minutes) |
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| 10:30 | Speaker Name (Cadence) (30 Minutes) | |||
| 11:00 | Refreshments and Networking | |||
| 11:30 | User Presentations | Training Session 1 | UVM for AMS Verification | |
| 11:30 | 10 years of Verification Challenges Mike Bartley, Tessolve Semiconductor Ltd (10 Minutes) RISCV CPU Verification - Opportunities and Challenges | What Can Formal Do For Me? Doug Smith (Doulos) (60 minutes) (Gold Sponsor) | Renesas’s Submission to the UVM-(A)MS working group
Peter Grove Steven Holloway (Renesas) REMOTE |
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| 11.40 | RISCV CPU Verification - Opportunities and Challenges Divyang Agrawal, Tenstorrent, Inc (30 Minutes) | |||
| 12:10 | Validation of Hybrid Architectures Suneil Mohan, Intel Corporation ( 20 Minutes) | |||
| 12:30 | Lunch and Networking | |||
| 13:30 | A Modern Fable: The Lost Art of Processor Verification Larry Lapides (Imperas Software Ltd.) (30 Minutes) Platinum Sponsor |
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| 14:00 | Advanced RISC-V Verification Technique Learnings for SoC Validation David Kelf (Breker Verification Systems) (20 Minutes) Gold Sponsor |
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| 14:20 | Improve the Quality of the Testbenches using specialized PySlint solutions Balram Naik Meghavath (Broadcom Ltd) (20 Minutes) |
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| 14:40 | Verification by Documentation Hemendra Talesara (Independent Board Member) (20 Minutes) |
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| 15:00 | Refreshments and Networking | |||
| 15:30 | Latest topics in Verification | Training Session 2 | VHDL Verification | |
| 15:30 | Leveraging AMS verification and DMS verification for efficiency and quality in Mixed-signal designs Aditya Devarakonda NXP Semiconductor (20 minutes) | Using Non-Determinism with Formal? Doug Smith (Doulos) (60 minutes) (Gold Sponsor) | Faster than “Lite” Verification Component Development with OSVVM Jim Lewis (SynthWorks Design Inc) (60 minutes) | |
| 15:50 | Sigmasense (20 Minutes) | |||
| 16:10 | Methodology focused testbench generation Benjamin Delsol – UVMGEN (20 Minutes) |
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| 16:30 | Event Closes | |||
