Gilboa Alin, Emilia Katz (Intel)

Formal-Verification (FV) plays a crucial role in the verification methodology of chip design. Establishing a robust signoff methodology is essential for FV to become a mainstream validation approach. The primary challenges/risks in FV include being overly constrained by assumptions, and assertions that do not cover the entire design. FV tools can create automatic cover points and attempt to verify that they are reachable and checked by at least one assertion. However, the number of cover points can reach hundreds of thousands and many of them can be unreachable or remain unchecked. Indicating which of them are hiding bugs is the main challenge in FV sign-off. In this presentation, we explore this topic and propose a solution for efficiently and reliably cleaning violation reports to facilitate sign-off.

Key Points:

• Running coverage checks is insufficient without a proper clean-up methodology.
• EDA tools can create and run coverage checks, but the clean-up process remains manual.
• Our flow helps achieve nearly 100% clean-up of coverage checks.

Gilboa Alin is an FV expert in the CPU department at Intel Israel, responsible for signoff and convergence methodologies. With over 25 years at Intel and more than 11 years of experience in FV, Gilboa has expertise in both execution and flow development. Gilboa holds a BSc and a Master's degree from the Electrical Engineering faculty of the Technion – Israel Institute of Technology. Additionally, Gilboa established and maintains the FV-Israel group of engineers, organizing local conferences and other activities for this community.

Emilia Katz is an FV expert in the CPU department at Intel Israel. Emilia holds a PhD in Formal Verification from the Computer Science faculty of the Technion - Israel Institute of Technology. Since completion of the PhD studies in 2011, Emilia has been holding several positions at Intel, ranging from development of verification and simulation tools to definition of FV methodologies and reusable kits.