Job Description

Position: DFT-Manger- Design Engineering

Experience: 12+ years relevant experience.

Location -  India

Education: B.Tech/M.Tech

To be successful in this role you will:

Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Design  for Test  skills  and Tools .

Technical Skillset Required:

·         Good knowledge in DFT Skills

·         Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS .

·         Prior experience in Synsopsys or Cadence or Mentor tools  Like Tetramax, Modus ,Tessent  and DC tools

·         Hands on in MBIST insertion and simulation

·         Knowledge  on JTAG is an added advantage .

·         Good Simulation debugging skills

·         Technical Documentation: uArchitecture Specification, SoC Integration Specification

·         Good exposure to Scripting skills like Perl or Python or Shell or TCL .

About us:

Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions.

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide,

Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.