Center of Excellence

Features like capturing DUT Pin List, Pin Specifications, and assigning Tester Resource are built into the tool. Every stage of the feasibility process is peer reviewed and approved by the TEST manager at appropriate stages. FEAST also has the capability to estimate Test Time, Coding, Debug, and correlation time for a given test list in a much quicker way. FEAST not only improves the efficiency of doing a feasibility study but also to do it more accurate.

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The tester which addresses the challenge of cost efficiency by maintaining scalability and increasing ATE longevity. The RF front-end switch is a growing market predominantly in the mobile phone sector and there is a high demand in the industry for reduced test costs for such switches. The tester built by Tessolve was able to provide >50% lower test times as compared to legacy ATE via a quad-site test solution. The tester is capable to test upto 6GHz RF front-end switches and is scalable to octal site testing.

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The image sensor is a growing market predominantly in the mobile phone sector and there is a high demand in the industry for reduced test costs for such sensors. The tester built by Tessolve was able to provide 30% lower test times as compared to legacy ATE. The tester is capable to test 256 pairs of LVDS lines up to 800Mbps speed. Add-on features like structural patterns up to 128 M scan depth are also integrated. We have developed an Image processing library using C# that is capable to detect any fault in the image captured.

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Including the capability to Characterize DDR5, and USB4 and could do advanced measurements like ISI/Crosstalk/Jitter Analysis along with de-embedding and equalization techniques. We have the software licenses to do TX/RX Compliance parameters up to DDR5/PCie Gen6/USB 4 etc.

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Pattern bring-up and BIB board bring-up activity will take 2 to 6 weeks. During this time HTOL oven is ideal and not effectively utilized. To overcome this we have Designed and developed an HTOL Pre station which is stand-alone and can be used for bring-up activities during this time HTOL oven can be used for other project execution. By implementing this Pre station, HTOL equipment can be effectively utilized. Requesting the sales team to use this info during customer interaction.

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With the Innovative way of component placement and also customized CBIT circuitry (NC/NO technique) we managed to achieve a 16-site ETS800 solution which helped to achieve ~98% parallel test efficiency resulting in Test cost reduction.

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A live demo of Flutter-based applications on AM62X was shown for Internet Radio, an automotive cluster, and an animation screen. TERA unit with industrialized design for automotive gateway has been showcased. Some of these demos were also showcased in Embedded World, NXP Tech Days, and CES. The S32G and AM62X SoM are SMARC 2.1 standard ones and have a Nano ITX size application board designed by Tessolve. The IMX8MPLUS SoM is the first OSM standard SoM module developed by Tessolve Embedded System Group. These SoMs have high-performance multi-core CPUs and dedicated MCUs with a rich set of peripheral interphases including High-speed memory, GBE, Multiple CAN, LIN, SERDES, and Multimedia interfaces. The SoMs are suitable for Automotive gateway and Industrial IoT applications and can be easily customized for the optimum requirement of customer needs. The TERA box is field tested and qualified. All the SoMs are supported with the required firmware for the peripheral devices.

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Traffic sign detection is one application that alerts the driver to take action. We implemented the application and tested it with Matlab in lab.

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We want to develop algorithms for the State of Charge, State of Health, and Active and Passive cell balancing algorithms. we had made requirements and designs for SOC & SOH.

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There is a demand for ensuring safety standards throughout the life cycle of vehicle development. ISO 26262 is an international standard for functional safety in the automotive industry. The ISO 26262 standard ensures that sufficient levels of safety are being met and maintained throughout the vehicle lifecycle. One of the prerequisites for entering the automotive sector is to get ISO26262 certification for all BUs at Tessolve which gives confidence to the customer that we are complying with the automotive standards and avoiding costly recalls & reputational damage due to safety hazards. Tessolve is presently working on training the Engineers on ISO26262 standards & getting process certification to meet customer requirements.

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Digitization of analog metering using AI Optical Character Recognition, Early Failure detection of a machine before the system break using Predictive Maintenance AI and many more. Those solutions are cost and power-optimized and respect privacy. The proposed approach is in two steps: Step1 : Check with a PoC that AI can solve the customer issue: A feasibility study to validate AI algorithm meet expectation criteria in term of reliability and predictability. Step2 : Complete development to integrate AI into the system.

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Our TSoC1 solution leverages these features for diverse applications, including Automotive, IoT, Mobile, Cloud, Data Center and Embedded Systems. TSoC1 has necessary peripherals such as USB, DDR3, Ethernet, and more, providing a fast and cost-effective market entry. TSoC1 is verified with C-tests and UVM, and its design and test environment can be easily adapted. With a projected 25% CAGR growth and a market size of 500 million USD, RISC-V offers endless opportunities.

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Each platform has its own language for specifying tests, which are often composed by different teams as well, and too much time and effort are spent recreating the same test information throughout a project. The Portable Stimulus Standard (PSS) was developed to solve the portability challenge. PSS allows tools, to automate test generation that is portable across vertical reuse(IP, Block, subsystem, and SoC level) and horizontal reuse(Simulation, emulation, FPGA prototyping )and maximize test coverage. Tessolve has already developed significant expertise in creating a PSS model and can support companies in their SoC verification.

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where we build systems from discrete "chiplets" and connect them inside a package This introduces challenges in the way we test design and test chiplets and the SiP to ensure we can get the required final yield numbers within acceptable test times. Tessolve has already developed significant expertise in this area and we can support companies on their transition from SoC to chiplets and SiP.

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designing IC Packages and PCBs for proper functionality is important and SI/PI simulations play an important role in design sign-off. At Tessolve we have integrated SI/PI process with the design flow to ensure optimized design output, equipped with infrastructure and software to address technology demand.

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An AI-based tool is under development to automate this assignment, using matching algorithms, following all constraints, and with a target to have routing done with minimal PCB layers and routing length. The tool is also expected to do auto-routing as well which will significantly reduce PCB design cycle time. The target completion date for the tool is May '23 and when successfully deployed the expected reduction in an ATE board cycle time is min 10%.

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