SystemVerilog Assertions (SVA) are a powerful language construct used in the verification of electronic designs. However, SVA syntax can be daunting to nonexperts, making it hard for new users to ramp up in verification tools and find bugs early in the verification pipeline. Advancements in linguistic generative intelligence, particularly large language models (LLMs), present an opportunity to automate SVA code generation from natural language descriptions, reducing manual effort and errors. Tune in to this presentation to learn how Cadence is integrating generative AI into its tools – particularly Jasper – to help users write SVA properties while also improving the results given by off-the-shelf foundation models.

Key Points:

• Generative AI presents an opportunity to automate the creation of SystemVerilog Assertion code, which can be daunting to nonexperts
• Results from off-the-shelf LLMs can be improved using different techniques that make it more accurate and efficient
• Direct integration into Cadence verification tools is key to improve the productivity and experience for our users

Paula Mathias is a Principal Product Engineer at Cadence with more than 9 years of experience working with product development, project management and software quality. She holds an MBA in Data Science and Analytics from University of Sao Paulo and is passionate about communication and interpersonal skills. She leads the development of generative AI tools in Jasper, as well as other core formal domains.