Agenda (BST):
| Conference: | DVCLUB Europe | Analog Mixed Signal Verification |
| Speaker: | Peter Grove, Renesas |
| Speaker Title: | A Mixed-Signal Universal Testbench for RTL/DMS/AMS (UTB) |
| Abstract: | Today’s chip level simulations utilize more RNM/DMS in addition to the classical DV/AMS to get enough verification coverage within the project timescales. Devices have become more complex meaning RNM/DMS is the only way to verify the system or device in any reasonable timescale to get the product to market. RNM/DMS techniques have expanded enough to model analogue blocks at a reasonable level, for example the User-Defined-NetType introduced in SV-2012. A key goal for most companies is to merge the two testbenches (DMS/AMS) and verification framework into one setup, of course to save money! A Unified Testbench (UTB) for mixed signal devices is required meaning that most of the information about the hierarchy needs to come from the schematic capture environment. This presentation will show how a UTB can be done in Virtuoso.
Key Points:
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| Speaker Biography: | Peter has worked in the industry starting back in 2001 when he joined a small company called Wolfson MicroElectronics, where he was project lead for more than 15 production devices. Since then Peter has only worked at one other company, Nujira, before joining Dialog (now Renesas) at their Edinburgh office. Peter has been with Dialog since 2014. Peter’s background has been main digital design but has over the years taken charge of many large mixed signal devices that are in volume production and been exposed to enough analogue design work to appreciate the issues they face in verification. Peter has an eye for looking for ways in which techniques can be done to improve chip level coverage, simulation runtime improvement to name a few. Peter is also in a unique position that during his days at Wolfson he was a key player in defining their schematic/Layout tool set with integrated revision control. This has allowed Peter to gather a large number of skills not just in design work but in all the backend flows and EDA tools, understanding different netlist types and how the tools work.
Peter’s technical interests are mixed signal and analogue verification methodologies, design flows. Peter also is an Acellera SystemVerilog-AMS committee chair, UVM-AMS member/key contributor making sure the ‘users’ feedback on the language is considered and not what the vendors just want to support. |
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