AFCML: Accelerating the Functional Coverage through Machine Learning within a UVM Framework

As system complexity continues to increase, there is a growing need for more effective verification methods. Recently, the AI has revolutionized the Design Verification methodologies. In this presentation, we aim to present that how effectively machine learning techniques can be used to pinpoint the most relevant stimuli from a broad set for a particular design within the UVM environment. By examining the design's features and the effects of various stimuli, the machine learning system strategically generates the most impactful stimuli, thereby enhancing the efficiency of the verification process. With the deployment of the machine learning model, the improvements in transaction efficiency of 49 percent is achieved and a notable decrease in the time is achieved to achieve 100% functional coverage closure.

Dr. Haroon Waris is a distinguished Professor at the Institute of Space Technology (IST), with over 15 years of experience in pioneering semiconductor solutions for industries such as telecommunications and automotive. A recognized leader in his field, Dr. Waris specializes in IP/SoC verification, FPGA development, hardware security, and AI-driven hardware accelerators.

With a strong commitment to fostering innovation, Dr. Waris has mentored countless engineers and researchers, inspiring the next generation of leaders in semiconductor and hardware design. His prolific career includes several patents and numerous publications in prestigious journals and conferences, highlighting his groundbreaking contributions to technology advancement and hardware security. Beyond academia, Dr. Waris actively engages with emerging technologies and is dedicated to sharing his expertise with the broader engineering community. His passion for innovation and excellence makes him a highly respected figure in both industry and academia.