The Verification Futures conference has always provided a unique blend of conference presentations, exhibitions, training and industry networking sessions for discussing the challenges faced in hardware and software verification thus providing a unique opportunity for end-users to define their verification challenges and collaborate with the other engineers and vendors to create solutions. In 2025 Verification Futures UK is expanding to include the use of AI/ML in IP/SoC, FPGA and Mixed Signal designs, as well as new tracks for UK Engineering students and UK-based semiconductor start-ups.
Event at a Glance
Tuesday, 01 July 2025 – Full day conference, exhibition and networking event
Reading (UK) & online
FREE to attend conference In-Person or Online
Conference Program
| 08:30 | Exhibition open and student posters available for viewing | Slides | Videos |
| 09:25 | Conference starts | ||
| 09:30 | Keynote speaker - Sean Redmond – Silicon Catalyst | ||
| 10:00 | Conference Sponsor - Platinum Plus - Cadence | 10:30 | Break - Exhibition open and student posters available for viewing |
| Verification | |||
| 11:00 | Main Morning | ||
| 11:00 | Main Morning Synopsys – Platinum Sponsor | ||
| 11:30 | VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL Anna Duque Antón (RPTU Kaiserslautern-Landau) |
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| 11:50 | A novel formal verification solution to Non-convergence Surinder Sood, ARM | ||
| 12:10 | Speaker | ||
| 11:00 | TBC (Breakout) | ||
| 11:00 | Speaker | ||
| 11:30 | Speaker | ||
| 11:50 | Speaker | ||
| 12:10 | Speaker | ||
| 11:00 | Training Engineers in work | ||
| 11:00 | Doulos Training (topic TBD) | ||
| 13:30 | Mixed Signal | ||
| 11:00 | Mixed Signal Platinum Design? Sponsor speaker? | ||
| 11:30 | Speaker | ||
| 11:50 | Speaker | ||
| 12:10 | Speaker | ||
| 11.00 | UKESF | ||
| 11:05 | UK ESF Stream for invited students | ||
| 11.00 | Design | ||
| 11:00 | AI/ML in Design Flows Platinum Design Sponsor speaker | ||
| 11:30 | Speaker | ||
| 11:50 | Speaker | ||
| 12:10 | Speaker | ||
| 11.00 | FPGA Verification | ||
| 11:00 | FPGA Test Benches Platinum Design Sponsor speaker | ||
| 11:30 | Speaker | ||
| 11:50 | Speaker | ||
| 12:10 | Speaker | ||
| 12:30 | Lunch - Exhibition open and student posters available for viewing | ||
| 13:30 | Afternoon Verification Session | ||
| 13:30 | Platinum Verif Sponsor Speaker | ||
| 14:00 | Gold Sponsor Speaker | ||
| 14:20 | Gold Sponsor Speaker | ||
| 14:40 | Gold Sponsor Speaker | ||
| 13:30 | Mixed Signal | ||
| 13:30 | Platinum Sponsor Speaker? | ||
| 14:00 | Speaker | ||
| 14:20 | Speaker | ||
| 14:40 | Speaker | ||
| 13:30 | UKESF | ||
| 13.30 | UK ESF Stream for invited students | ||
| 13.30 | AI Design IP | ||
| 13.30 | Platinum Design IP Sponsor Speaker | ||
| 14.00 | Mrudula Gore Imgtec | ||
| 14.20 | Speaker | ||
| 13.40 | Speaker | ||
| 13:30 | Verifying IP designs in FPGA | ||
| 13.30 | Platinum FPGA Sponsor Speaker | ||
| 14.00 | CocoTB | ||
| 14.20 | HDLRegression: A reliable and efficient tool for FPGA regression testing Marius Elvegård (Inventas) |
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| 14.40 | Speaker | ||
| 15:00 | Break - Exhibition open and student posters available for viewing | ||
| Advance Verification Topics | |||
| 15:30 | Main Afternoon | ||
| 15.30 | Multisim: simulate your RTL with real multi-threaded speed Antoine Madec (Axelera AI) |
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| 15.50 | Mrudula Gore Imgtec (colleague) | ||
| 16.10 | AFCML: Accelerating the Functional Coverage through Machine Learning within a UVM Framework Haroon Waris (Institute of Space Technology (IST)) |
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| 15:30 | CPU/RISCV Verification (Breakout) | ||
| 15.30 | Configuring Spike to model your RISC-V implementation Mike Thompson (OpenHW Founation) |
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| 15.50 | Formal Verification of Security-Properties on RISC-V Processors Christian Appold (Denso Automotive Deutschland GmbH) |
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| 16.10 | 𝜇CFI: Formal Verification of Microarchitectural Control-flow Integrity Katharina Ceesay-Seitz (ETH Zurich) |
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| 15:30 | AI in DV | ||
| 15.30 | Kerstin Eder – Bristol University | ||
| 15:30 | Mixed Signal | ||
| 15.30 | Speaker | ||
| 15.50 | Speaker | ||
| 16.10 | Speaker | ||
| 15:30 | UKESF | ||
| 15.30 | UK ESF Stream for invited students | ||
| 15:30 | Design | ||
| 15.30 | AI IP in SoC Jörg Paul, Dreamchimp | ||
| 15.50 | Speaker | ||
| 16.10 | Speaker | ||
| 15:30 | FPGA | ||
| 15.30 | top-level verif for FPGA with AI Speaker | ||
| 15.50 | Speaker | ||
| 16.10 | Speaker | ||
| 16:30 | Drinks and Pizza, student poster competition prize giving, sponsor gift raffle draw | ||
| 17:00 | End of conference |
Sponsors
VF2025 was made possible through the generosity of the following sponsors. If you would like to become a VF2025 sponsor please Contact Us.
