A pragmatic approach to improving your FPGA VHDL verification

A good architecture is very important for FPGA design, but it is in fact equally important for verification of complex FPGA design. The verification architecture determines the verification efficiency and the product quality for complex designs. The difference between a good and a “normal” verification architecture could be many hundred hours, and for medium to complex designs even as much as a couple of thousand hours. The only good thing about this - is that you can easily do something about it. UVVM was made exactly for this and is free and open source - and used by 35-40% of all FPGA VHDL designers world-wide. A new ESA (European Space Agency) project has just been initiated to extend UVVM even further.

In this presentation, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously. We will show testbench examples for a simple interrupt controller, for AXI, for Avalon and more - to illustrate how UVVM will help allow pragmatic and simple verification of both simple and complex DUTs.

Espen Tallaksen is the CEO of EmLogic, in Norway. Espen is also the author and architect of the Open Source UVVM (Universal VHDL Verification Methodology). He has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement, and he has given lots of presentations at various international conferences with great feedback. He is also giving courses on FPGA Design and Verification.