Accelerating RISC-V testbench development with open source RISC-V RTL and emulation

Today’s shorter product time to market makes silicon verification runway shorter. Tenstorrent is working on CPUs based on RISC-V architecture for many AI applications. Since this is an emerging processor environment having RTL ready is not an easy task. Once RTL is available the testbench should be ready for both simulation and emulation workloads. Also, we should have all test collaterals ready to go, which involves firmware, drivers, applications etc.

At Tenstorrent we solved this problem by adopting RTL from RISC-V open source. This enabled us to shift left the emulation and simulation testbench creation. We use a standard memory interface, AXI, standard instruction interface, RISC-V Formal Interface (RVFI), and the open source CVA-6 RISC-V cpu to develop testbench architecture and collateral in advance with full architectural instruction-by- instruction checking. This helped us complete the testbench development and test infrastructure ready without our custom CPU RTL. When the inhouse RTL is ready, we could be able to replace our custom CPU RTL with open source CVA-6 processor.

This methodology helped us significantly shift left the testbench and test infrastructure readiness. Due to this, we could able to innovate in the area of test collateral creation, making emulation ready infrastructure and were confident to run application level tests the minute RTL was available. We used ZeBu for emulation work on this accelerated testbench creation with open source RTL.

Varun is a design verification engineer with more than ten years experience in the CPU space. He has a passion for leveraging new technologies to speed-up the verification process from pre-silicon to production.