OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, scripting API, and co-simulation capability that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries you can create a readable, powerful, and concise testbench that will boost productivity for either low level block tests (unit tests) or complex FPGA and ASIC tests.

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, scripting API, and co-simulation capability that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries you can create a readable, powerful, and concise testbench that will boost productivity for either low level block tests (unit tests) or complex FPGA and ASIC tests.

OSVVM has grown rapidly during the COVID years, giving us better capability, better test reporting (HTML and Junit), and scripting that is simple to use (and works with most VHDL simulators). This presentation will show how these advances fit into the overall OSVVM Methodology. Looking to improve your VHDL verification methodology? OSVVM provides a complete solution for VHDL ASIC or FPGA verification. There is no new language to learn. It is simple, powerful, and concise. Any VHDL engineer can write either tests or verification components.

Each piece/capability of OSVVM can be used separately. Hence, you can learn and adopt pieces as you need them. Maybe your EDA vendor has suggested that you should be using SystemVerilog for verification. According to the 2022 Wilson Verification Survey [1], for both FPGA design and verification, VHDL is used more often than Verilog or SystemVerilog. Likewise, in the survey you will find that OSVVM is the #1 VHDL verification methodology. [1] https://blogs.sw.siemens.com/verificationhorizons/2022/11/21/part-6-the-2022-wilson-research-group-functional-verification-study/

Key Points:

OSVVM + VHDL provide

• A structured, transaction based testbench environment in which any VHDL engineer can write VHDL testbenches and test cases for both simple unit/RTL level tests and complex, randomized full chip or system level tests.
• Buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering that are simple to use and work like built-in language features.
• Powerful verification data structures that provide unmatched test reporting with HTML for humans and JUnit XML for CI tools.

Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.

Whether teaching, developing OSVVM, consulting on VHDL design and verification projects, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.