High Speed pattern delivery using 1149.10

The cost of test is rising as a percentage of manufacturing costs, fuelled by concerns about reliability of advanced-node designs in automotive and data centres, as well as extended lifetimes for chips in those and other markets. Complex technologies have increased from SoC to System-In-Package (SIP) and also software complexities. This complexity results in more asynchronous interfaces, more interactions among power, clock and thermal domains as well as software and hardware. SLT is the trending solution to eliminate the defective parts not caught in normal manufacturing structural tests. Structural testing is the test method of choice for all Manufacturing test delivered by ATE. Parallelism in ATE is limited due to tester resources, handler capability and other infrastructure issue. This paper talks about utilising the possible massive parallelism capability available during SLT to reduce test cost and faster pattern delivery to DUT for load and unload operation during structural testing using 1149.10 to reduce test time.

Key Points

• Structural tests are the only option to test digital device to screen out maximum manufacturing defects and also have a quantitative measure of screening efficiency.
• Due to complexity of SOC’s, it’s uses, the need for high reliability in safety application etc, Industry is moving towards SLT, sampled SLT if not 100% SLT.
• The high parallelism and low infra cost of SLT can be used to reduce test cost if we can deliver patterns faster to the DUT and let the high speed DUT Internal busses distribute data and test partitions parallelly.

Anand Muthaiah has been with Tessolve for more than 12 years in multiple roles. Currently he heads the COE for test engineering. Anand Has a master’s degree from University of South Florida and has over 30 yrs of experience in the semiconductor industry. He has extensive experience in post Si engineering and manufacturing activities.