Facilitating the qualification of Design and Verification changes by DV teams on daily basis is demanding. Engineers working on various (sub-)blocks of an IP during the development phase of the project is demanding as the complexity grows.

Multiple commits from different team members without right qualification is backbreaking and could cause prolonged debug cycle directly impacting project schedules. A single bug in any commit may contaminate the entire design verification suite resulting in cascading effect over the days.

A captious regression is thus essential for big IP verification but it can become complicated due the ever growing complexity and dependability on various interconnected blocks E.g. different views of verification and design functional blocks. It is unreasonable for anyone to know / extract the tests based on the changes being made.

It is infeasible for an user to know the connected and related blocks and functionalities. A Regression Flow Tool is being developed to extract a high quality test suite for the qualification regressions based on the changes made by a design or verification engineer. This takes various parameters and factors into consideration making it project independent and highly re-usable.

Key Points:

• Improved quality of qualification regression.
• Improved quality of design and verification commits

Rajendra Prasad has 20+ years of experience in verification. He started his journey as architect for 8 and 16-bit microcontrollers. He then moved to front end design for Hard Disk Drive applications followed by verification of TriCore, CPU used in Aurix products of Infineon. He currently the head of Verification at Infineon Bristol.