System-Level Test

Key Factors Driving System-Level Test (SLT) in the Semiconductor Test Flow

Lower technology nodes drive a higher number of untested transistors.
Concurrent scenarios are driving complex test scenarios.
Lower VDD creates higher concerns for guardband stack and yield overkill.
DVFS (dynamic voltage and frequency scaling) explosion and PVT (process voltage and temperature) corners driving too many test scenarios.
Conventional test methods no longer catch new possible faults for lower technology nodes.
Testing for customer-specific Use Case is becoming a key need for the devices that are used for mission-critical applications such as Automotive along with the need for 0 DPPM quality levels.

System Level Test

Products like CPU, GPU, AI, and Microcontrollers are generally designed for wide applications. While these products are manufactured and tested in volume, the focus is more on getting the various blocks that are present within the IC tested for a pass and fail and classify the device a pass, when all the blocks in the device pass.

Whereas in a real application for example CPU/Microcontroller used for automotive, the device needs to be tested along with the other supportive ICs such as PMIC, Memory, Display, and other power electronic and customer-specific firmware. It is important to mention that the support ICs mentioned may not be from the same manufacturer.

Testing for customer-specific Use Case is becoming a key need for the devices that are used for mission-critical applications such as Automotive along with the need for 0 DPPM quality levels is driving the need for more SLT.

Why SLT is Needed?

System Level Test (SLT) enables IC manufacturers to emulate the final user environment to test software and validate connections between IP blocks. It is a more effective and less expensive way to test I/O protocol stacks, IP block to block interfaces and different clock, power, thermal and hardware/software domain interactions.
The SLT insertion isn’t appropriate for every chip. It tends to be used for system-oriented chips in markets where quality is critical.
This is especially true where the external environment during testing is important. Temperature and voltage can be controlled on a per-site basis during SLT, so this can be a lower-cost way of ensuring that chips perform properly under all conditions.

Verticals where SLT is key.

Three markets have demand for SLT — Smartphones, Automotive, and high-performance computing. They do so for different reasons and drive different test conditions.

Smartphone Chips

Smartphone chips usually will be tested at room temperature. The goal of this insertion for these high-volume chips is to ensure the highest quality to minimize equipment returns.

Automotive Chips

Automotive chips are more demanding and make use of automatic temperature control. They need to be tested from -40°C to 150°C to ensure chips can survive these environmental extremes in a safety-critical system.

High Performance

High Performance chips Makers of chips for high-intensity computing, on the other hand, are mostly concerned with ensuring their chips don’t overheat during test. So rather than the test site enforcing a specific temperature, the goal is to provide enough cooling to keep the Junction temperature below 125°C. Cold testing isn’t generally needed because the chips will quickly self-heat once started up.

Why Tessolve?

In the ever-changing landscape of the Semiconductor Test, System-level testing (SLT) has emerged to be one of the most prominent methodologies for production testing. We at Tessolve take the utmost pride in introducing SLT for Volume as one of the Centre of Excellence (COE) initiatives for emerging technologies in the Test Business Unit (BU).

Tessolve’s SLT Solutions

Software Infrastructure

The engineering test capability saving both cost and time, A user-friendly graphical interface (Windows) system provides a quick and easy device setup changeover, simplifying the process and increasing its efficiency.
System Level Test Applications (SLT)
Software configurable binning
Allows for maximizing the test socket lifetime
Protection against IC double stacking and incorrect device placement orientation
Continuous automated re-test capabilities

Test Handler is an automated pick & place handling system ideal for engineering samples. With its focus at the System Level Test (SLT) platform, handling system can handle a large variety of device types. With the wide range of chip sizes supported, it also enables high throughput to support the testing of smartphones, tablets, PC’s and automotive chipsets allowing for temperature control capabilities from ambient to temperature ceilings of 125℃. It’s ideal compact size and product versatility, combined with its low cost per test site allows for expandable test applications throughout your test floor.

Hardware Development

Host PCs (Site 1 to 4 Test PCs) are identical builds, this is where SLT test program runs.
Handler PC controls handler robot movement, thermal control Communicates to Host PCs via Ethernet/TCPIP protocol.
SLT handler for high volume/multi-site IC testing at system level. It is capable of handling packages of various types including QFP, TQFP, BGA, PGA, etc. The handler uses pick and place technology to pick up devices from JEDEC trays, move them to the test site, then move them to the appropriate bin after test. It features a 90-degree device rotation which is required for various pin one orientations.
SLT handler can test up to 4 devices in parallel at high temperature with ATC (Auto Temperature Cooling) ranging from 50˚C to 125˚C.

Overview of iEEE1149.10

Using IEEE 1149.10 to accelerate SLT

SLT is compatible with IEEE 1149.10, the standard that defines high-speed test access ports and data distribution architecture for on-chip test structures. Together, SLT and IEEE 1149.10 can provide higher and more cost-effective test coverage for complex and non-deterministic ICs with the following benefits.

High-Speed Test
Reduction in Complexity and Test Pins (Reusability of HSIO)
Error Free Application of Test Data
Multiple PEDDA HSTAP implementations for higher bandwidth support

As a part of the PoC1 for IEEE 1149.10 DUT PEDDA and Tester PEDDA IP implementation is done on the Genesys2 FPGA board. The boards are communicating the Test and Response through the High-Speed FMC connection. The following architecture gives an idea about FPGA implementation on the DUT and Test side of the FPGA.

DUT FPGA

Test FPGA