With the advent of multi-core RTL simulators and Emulation Platforms, the testbench has become a bottleneck in the functional verification of hardware. Emergence of RISC-V and opensource hardware has also increased the scope of verifciation on the cloud as a key enabler of the development cycle that includes continuous integration as an essential component. Based on the experience gained while coding a multicore-enabled eUVM implementation of RISCV-DV that generates 500,000 randomized intrunctions in a second, we take a look at how parallelism and other High Performance Computing (HPC) techniques can be adopted for crafting accelerated testbenches for Functional Verification.

Key Points:

• Testbenches are fast becoming a bottleneck for Multicore Simulators and for Co-Emulation
• eUVM implements a multicore version of UVM with ABI compatibility with C/C++
• An HPC implementation of RISCV-DV generates randomized RISC-V test vectors at a rate of 500,000 instr/sec, over 50X faster compared to the original SystemVerilog implementation

Puneet Goel is the co-founder and CTO at Coverify, where he is crafting opensource tools, libraries, and VIPs for Hardware Verification. Currently, Puneet is leading the hardware verification team at IncoreSemi to create verification solutions for Incore’s state-of-the-art RISC-V processors.

Puneet has over twenty-seven years experience in the VLSI industry. He was an early adapter of SystemVerilog. He has also participated as a member of the IEEE technical committee for SystemC standard. He has multiple DVCon publications and a couple of patents to his credit.