Introducing Smart Verification: Unleashing the Potential of AI within Functional Verification

Design and verification teams working on Next generation IC (ASIC and FPGA) are facing increasing challenges with growing design and verification complexity, exacerbated by skills and engineering resource shortage which is in turn impacting their productivity. With recent advances in AI, many are looking to this technology to help improve productivity. In this session, you will learn Siemens EDA’s strategy for leveraging AI in functional verification by harnessing key pillars: EDA Knowledge, Data, and AI Expertise; and you will be introduced to EDA tools that are leveraging this strategy to resolve these challenges.

Gabriel Chidolue is a Product Engineering Manager in the Design Verification Technology group within Siemens EDA, a part of Siemens DI SW. He has over 20 years’ experience in Digital design and verification. His main responsibilities include creation and deployment of verification methodologies, flows and solutions in close collaboration with R & D, Siemens EDA Customers and Partners. Prior to joining Siemens EDA (formerly Mentor Graphics), he was an Application Specialist, working on various EDA tools including Logic Synthesis, Digital Simulation and Debug, and Formal Equivalency Checking. Mr Chidolue holds a B.Eng in Electrical Engineering from University of Nigeria, Nigeria and an M Sc in Concurrent Engineering for Electronic Product Design from Bournemouth University, United Kingdom.