Using Symbolic Execution to analyze Hardware TCP/IP Stacks
Based on HLS Development

Hardware accelerators developed based on High-Level Synthesis(HLS) are becoming increasingly popular in modern computing systems. Symbolic execution is a powerful technique for analyzing software programs, but its application to hardware accelerators developed with HLS presents some challenges. This paper explores the use of symbolic execution to analyze a real-world HLS-based hardware accelerator, hardware TCP/IP stack. We discuss the challenges encountered in this context, and propose feasible solutions to use symbolic execution to improve code coverage testing. Overall, this paper highlights the great potential of symbolic execution in analyzing HLS hardware accelerators and suggests directions for future research.

Mr. Nianhang Hu has been pursuing a Master’s degree at the University of Nebraska-Lincoln since 2022. He earned his Bachelor's degree in Electronic Engineering from Zhengzhou University in 2005. With extensive industry experience in chip functional verification and bring-up, he has worked at prominent companies including Foxconn, TI, and Nufront. Notably, he led a team of 20 firmware engineers for three years, achieving a 100% first-pass success rate and 98% functional test coverage in bringing up four ARM-based chips. His exceptional skills in both software and hardware debugging have been instrumental in his success.