Practical applications of machine learning in design verification and ISO 26262 practices

ML (Machine Learning) is transforming the way we work in a wide range of industries and this has been accelerated by generative AI (Artificial Intelligence) applications such as ChatGPT. In this presentation we investigate how ML and AI can potentially be applied in DV (Design Verification), from automation of requirements/specification analysis and test plan generation, through test bench creation and test generation, to debug and coverage closure. There is a very wide range of ML techniques available and this presentation first surveys those techniques and how they have been applied (successfully and unsuccessfully) to DV in both academia and in real projects. The objective is to better understand how to apply the most promising techniques to a wide range of DV activities to ultimately make DV both more efficient and effective. The main objective of the presentation is to give the audience a better understanding of what is achievable of applying ML in DV and to give practical suggestions on their adoption.

The integration of Generative AI (GenAI) into ISO 26262 practices represents a transformative approach to automotive functional safety. As the demand for safer automotive systems grows, it is essential to leverage strengths from other domains to enhance automotive safety practices. Recent advancements in Generative AI models and practices have opened new doors to innovative approaches. Beginning with an understanding of Functional Safety concepts, the trained AI model proves useful in Hazard Analysis and Risk Assessment (HARA), requirements management, Failure Mode and Effects Analysis (FMEA), Automotive Safety Integrity Level (ASIL) determination, and compiling compliance evidence The presentation features several noteworthy use cases where the trained AI model is particularly useful for the Functional Safety team.

Dilip has 10 years of industry experience as a design verification engineer and has worked extensively on verifying designs at full chip level as well as subsystem and IPs. Dilip has worked with leading semiconductor companies on world class products and has gained in-depth knowledge on the concepts of verification. Dilip currently works as a verification consultant for Xilinx-AMD and is involved in verifying the FPGA designs at full chip level