Memory Patterns – Reusable Stimulus for RISC V Memory Subsystem Verification

Verifying Memory Subsystem in CPU is hard. The design blocks span from Load store to caches, NOCs and to the memory. In RISC, the max access size is 8 bytes at the Load Store Unit. The caches operate on whole 64bytes (32byte) cache line size. DV challenges span across a) Coherency: The verification of Hit or Miss, Snoops on L1, L2 and L3. b) Memory ordering between LD, ST c) Data Forwarding from ST to LD, d) Aligned vs unaligned transfers e) NOC Latency modelling f) Complex address patterns. This presentation proposes a reusable Memory Pattern generator that can stress the memory subsystem from Unit level to full core level.

Vibarajan (Viba) Viswanathan has over 25 Years of experience in Semiconductor and EDA industry, mostly in Design Verification. Viba holds a bachelor’s degree in Electronics and Communication Engg., and a PG Diploma from UT Austin on AIML. His work experience spans across companies that include 0-In Design Automation, Synopsys, Mentor Graphics, Marvell Semiconductor, Samsung, Centaur and Microsoft. He was part of the pioneering team on Assertions and Assertion IPs, Formal Verification and Verification IPs. Viba’s domain expertise includes RISCV CPU/GPU Memory Subsystem, Load Store, Cache Coherency, Memory Ordering, Shader Core, Coherent Interconnects, CHI, DDR/LPDDR Memory Controllers. Viba is an avid follower of conferences and the various Verification Methodologies that include Constrained Random, Formal Property Verification, Assembly level instruction generation and AIML DV Use cases.