AI and GenAI for Verification Productivity

The chip and system design industry faces a growing productivity challenge, with complexity on pace to increase 100X over the next decade. The complexity is outpacing the industry’s ability to train new engineers, presenting companies with substantial risk. AI is being actively applied to the productivity challenge, showing great promise in improving efficiency by ten times or more. Cadence is further addressing this challenge through a series of advancements, which include accelerated compute, application of high-speed engines, and optimization with AI and Generative AI. EDA can benefit greatly by applying AI with the engineer-in-the-loop approach. This presentation will explore Cadence’s AI accelerators for debug and formal proof analysis. In addition, we will also examine how a Retrieval-Augmented Generation (RAG) integrated with large Language Models (LLMs) can significantly reduce LLM hallucinations. Finally, we will delve into the application of copilots for assisting verification engineers with documentation, specifications, and planning.

Paul has over 25 years of expertise in the design and verification of SoCs. His diverse career encompasses technical roles in corporate and field application engineering as well as technical and product marketing. Currently, Paul is focused on product marketing and management for Cadence’s Xcelium Simulator. Previously, he drove the application of IPXACT and Network on Chip at Arteris. During his 20-year tenure at Synopsys, Paul specialized in Verification IP and methodologies, evolving from Vera and VMM to SystemVerilog and UVM. His professional journey also includes positions at Compaq (HP), Intel, and Cirrus Logic. Paul earned his BSEE from Texas A&M.