A Holistic Approach to RISC-V Processor Verification

Processors using the open standard RISC-V instruction set architecture (ISA) are becoming more and more common, with an estimated 30% of SoCs designed in 2023 containing at least one RISC-V core. Whether licensing RISC-V IP and adding custom instructions, using open-source RISC-V IP, or building a RISC-V processor from scratch, verification of RISC-V processors is a task in the SoC project plan. With the variety of sources for the processor IP, the range of complexity and the span of use cases, a one-size-fits-all approach to RISC-V processor verification does not work.

This session will present a holistic approach to RISC-V processor verification. It will address processor complexity from microcontrollers to application processors to arrays of processors for AI accelerators, different levels of integration from unit to individual processor to processing subsystem to SoC and cover different scenarios depending on the source of the processor IP. Matching different technologies and methodologies to this multidimensional verification space is critical. In addition, we will elaborate on different decisions that go into the verification plan for RISC-V processors and review the different technologies and methodologies that are employed in a holistic approach to processor verification.

Larry Lapides is Executive Director, Business Development at Synopsys, responsible for the Imperas-branded products. Prior to Synopsys’ acquisition of Imperas Software Ltd. in 2023, Larry was VP of Worldwide Sales & Marketing and a member of the founding team. Before Imperas, he held several roles in sales and marketing including VP of worldwide sales during the run-up to Verisity’s IPO.

Larry holds a BA in Physics, with General Distinction in Physics, from the University of California Berkeley, a MS in Applied and Engineering Physics from Cornell University and an MBA from Clark University.