UVM for IP Designers—Moving Toward “Killing two birds with one stone”

In our hardware IP development methodology, designers typically put together a simple module-based directed-stimulus testbench to do the initial “bring up” of their RTL model, in an effort to verify basic functionality before handing off the design to a verification engineer for official sign-off verification. The verification engineer typically starts over and develops a constrained-random testbench using UVM. Often, due to the limited coverage of the bring-up testbench, we find ourselves in the unhappy situation of attempting to simultaneously turn on, by way of the UVM testbench, three pieces of non-trivial code: the Verilog RTL model, the UVM testbench, and the C++ golden reference model consulted by the UVM scoreboard. We began to wonder if there was a smarter way of working. Could we achieve more coverage at the bring-up stage by making UVM accessible and palatable to RTL designers, and then leverage the bring-up testbench as the starting point for the sign-off testbench? Would a testbench code generator tool help make UVM more accessible to designers? Our presentation summarizes our experience to date in pursuing these questions

3 Key Points:

• The initial bring-up of the sign-off unit-level UVM testbench can be expensive.
• Increasing the effectiveness of the IPdesigner’s bring-up testbench is one way to mitigate this expense.
• A testbench code generator can help make UVM palatable and accessible to RTL designers, and can therefore facilitate this increase in effectiveness.