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Careers

Positions Open @ Tessolve
Looking for a suitable opening in Tessolve? Here are the positions open currently.

Qualification : BE or M Tech in ECE, CS, Info Science, Medical, Mechatronic, IOT
Experience : 2 to 5 Years in Linux embedded system development / debug domain, advantage if completed 6 months course in Embedded domain and has good ARM/Linux-Yocto build/Raspberry Pi/ Arduino /Beagle Bone
No of Position :

Requirements :

  • Must be good in embedded C programming.
  • Candidate should have good understanding of Embedded Linux, SOC, platform based on ARM/Intel and has developed and debugged Linux drivers for embedded products, I2C, UART, WiFi, BT, Multimedia, sensors, USB, Battery charger, PMIC etc.
  • Excellent skill in SW development and SDLC, familiar with JIRA, source code control environments - github
  • Good in using In-circuit emulators, Scope, Logic analyzers, protocol analyzers, JTAG, ADB, Trace-32 debug tools.

Responsibilities :

  • Candidate will develop/debug Linux device drivers for mobile, IOT platforms
  • Candidate will work with leads/other team members to support in SOC/platform SW development and debug.

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Qualification : BE / M Tech in ECE or Instrumentation or Embedded electronics, Diploma in ECE
Experience : 2 to 5 Years
No of Position :

Requirements :

  • Should be a BE / M Tech. Should have good understanding of SOC, platform based on Intel / ARM and interfaces and Linux / RTOS.
  • Should have good knowledge of board bring up, debug and triage. Understand the boot sequence, fw debug, Configuration.
  • Good in using Scope, DMM, Logic analysers, protocol analysers, JTAG, ADB, Trace-32 debug tools, well versed in hw debug.
  • Should have good ARM / Linux-Yocto build / Raspberry Pi / Arduino / Beagle Bone or PC (Intel) BIOS / board level experience and board bring up.

Responsibilities :

  • Candidate will do functional validation, write test cases, automate and find bugs on SOC/platform fw or driver.
  • Work with Pre-Silicon and Silicon debug teams/emulation teams, debug- root cause issues and provide solutions.

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Qualification : ITI / Diploma in ECE / EEE
Experience : Minimum Experience / Freshers
No of Position : 6

Requirements :

  • Personnel required to work in shifts 24/7.
  • Personnel could be deployed for Onsite / customer place.

Responsibilities :

  • Personnel would be responsible for data collection on ATE / Bench.

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Qualification : BE / B.Tech / ME / M.Tech (Electrical & Electronics Engineering (EEE), Electronics & Communication Engineering (ECE)) - (Location - Bangalore, Job Type - Full time)
Experience : 1.6 - 4 Years
No of Position :

Requirements :

  • Candidates should have experience in any of the following areas :
  • ATE Test : ATE test engineers with experience in ATE level testing on Teradyne ( Catalyst/iFlex/uFlex/ Eagle etc), Advantest ( 93k,T2K), Nextest, SPEA etc.
  • PMIC: Power management systems design / debug / testing / integration of Buck/Boost/Buck-boost/LDOs, precision references, battery charge controllers, lighting systems, current sources and sinks and crystal oscillators
  • Mixed Signal: Experience with Mixed-signal blocks like ADC, DAC and PLL blocks and their measurement techniques such as INL, DNL, Gain and Offset Error, SFDR, THD+N, ICN, Jitter, Phase noise, Lock time etc
  • High Speed: Experience with High-Speed SERDES (USB, DDR, SATA, PCIe,SGMII/QSGMII, MIPI PHY , HDMI, LVDS,eDP).Knowledge on Signal Parameters like eye diagram, Overshoot, Undershoot, DC Threshold multi-crossing etc
  • Hardware Board Design: Fundamental understanding and hands-on experience with analog and digital electronics and help routing on PCB with SI analysis
  • FPGA: Design/Integrate application circuits using FPGA/Microcontroller programming and familiar with process like ICT, JTAG, I2C, SPI and AXI
  • System Level Testing: Extract the system level parameters of SOC’s/Application circuits or Transceivers. Determine the best way a test can be performed in order to achieve 100% test coverage of all components using different test processes. Designing test plans, developing test cases/scenarios/usage cases, and executing these cases.
  • Product Engineering : Burn-in board design/debug, Lot disposition, Yield analysis, TTR and quality improvement, experience working on tools like Datapower, spot fire Sedana, yield works, IC qualification like HTOL, HAST, ESD, Latchup
  • Debug skills :
  • Experience in troubleshooting and ability to resolve issues in test setup
  • Debug skills on ATE( Automatic Test Equipment)
  • Hands on experience in handling and debugging the hardware using DMM, Oscilloscope, Function Generator, Logic analyzer , Power supply.
  • Software Skills (Any of the following) :
  • Programming skills like C++/C-Sharp (or equivalent)
  • Knowledge on Labview/VEEpro /Python Automation software
  • Knowledge on Visual basic/ VBA/Matlab

Responsibilities :

  • Develop ATE test solution for semiconductor IC’s in different domains as Power management / Digital / Mixed signal or RF
  • Be a primary contact to interact with customer / vendors (design / support teams)
  • Work with design/DFT team to develop the detailed test procedure from device data sheet.
  • Develop and lead the hardware design activity (Probe cards / Final test load boards), develop schematics, provide placement / layout guidelines to PCB design engineer
  • First silicon verification and device bring up using ATE tools. Leading ATE’s from Teradyne, Advantest etc (Uflex, 93K etc)
  • ATE software development as per test procedure document (C, C++, Perl, VB etc)
  • ATE software development as per test procedure document (C, C++, Perl, VB etc)
  • Responsible for releasing the Final production quality test program to the customer - both wafer final test program.
  • Interact with the customer on a daily basis and provide status updates through e-mails and conference calls.
  • Responsible from the beginning to the Final test program release to production

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Qualification : BE in ECE / EEE
Experience : 3 to 5 years 
No of Position :

Requirements :

  • Tools Expertise :
  • Orcad, Concept HDL
  • Cadence Allegro, Altium/Pads
  • Design Expertise :
  • Complete understanding of Constraint Manager Settings
  • High Speed Interfaces Exposure
  • HDI, Blind/Burried via technology Exposure
  • Individual Contributor Ability

Responsibilities :

  • Schematic Entry as per customer requirement
  • Component library creation as per JEDEC standards
  • Component placement and Mechanical constraints consideration
  • IO and PD routing
  • Design checklist and review consideration
  • Manufacturing and Test files generation
  • Design Documentation

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Qualification : BE, MBA / equivalent
Experience : 8 - 10 yrs
No of Position :

Requirements :

  • Manages daily activities of the operational sales support function and sales support team
  • Managing the complete ERP / CRM sales process (customer enquiry,quote,order,execution and completion) , backend support and assist the sales team
  • Oversees workflow of all business processing including preparation of reports, charts, and other statistics to support and direct the sales department
  • Manages customer contracts, NDA’s and agreements
  • Assists with budget management to ensure expenses meet target goals.
  • Handle and resolve complex customer requests or complaints in
  • Develops and implements promotional events and interacts with external dealers to increase sales volume.
  • Providing Monthly Sales Info Sheet to Finance with pending info and Tracking
  • Familiar with a variety of the field's concepts, practices, and procedures.
  • Leads and directs the works of other sales team members.

Responsibilities :

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Qualification : B.E / M.E in Computer / Electronics
Experience : 6 to 8 yrs, 6-8 years of embedded s/w development. At least 4 years of hands on experience with ARM processors and SW tool chains
No of Position :

Requirements :

  • Development and verification of Boot loader and Hardware APIs for ARM Cortex M0/M3 based Low power SoCs
  • Setting up the tool chain, generating make files for firmware development
  • Work closely with Hardware designers and verification engineers for analyzing defining SW requirements
  • Hardware S/W co-verification
  • Silicon bring up/validation of ARM Cortex M0/M3 based Low power SoCs
  • Should be able to drive the demo/reference system design and development activities.
  • Should review overall SoC architecture and recommend efficient HW-SW system
  • Required Skills :
  • In depth understanding of ARM CortexM0/M3 architecture
  • Master’s/Bachelor’s Degree in electronics or electronics and communication engineering from a reputed university
  • In-depth knowledge of software tools for ARM processor like IAR, Kiel etc.
  • Good mathematical skills with digital signal processing background
  • Must have experience and strong fundamental knowledge of microcontroller and SOCs
  • Linux RTOS and Device Driver Development Experience.
  • Strong technical background in the field of embedded software development
  • Strong programming skills
  • Strong command over C and assembly programming language
  • Must have hands on debugging and development experience on micro-controller based application boards
  • Strong problem-solving skills and teamwork, Self-motivated, excellent verbal and written communication

Responsibilities :

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Qualification : BE in Mechanical Engineering
Experience : 3 to 5 years
No of Position :

Requirements :

  • Mechanical design of electronics products, assemblies and fixtures -Creating and modifying 3D models of electro-mechanical components with the help of Creo 3.0 or higher (solid model assembly, part, and drawing creation).
  • Strong working experience in Defining PWB outline, mounting, and I/O constraints of electronic circuit boards and flexible circuit interconnects and exchanging IDF/EMN files between mechanical and HW teams
  • Development and maintaining of Engineering (design and testing) documentation per ASME Y14.5-2009.
  • Should be able to work with top-down skeleton model structuring and master model design techniques within Pro/E
  • Should be able to design Sheet metal based on-board EMI shielding cans
  • Should be able to design CNC machined and stamped metal parts, injection molded plastics
  • Creating and modifying assembly and detailed part drawings -Configuration management including Bill of Materials (BOM) creation, Engineering Change Orders (ECO).
  • Strong knowledge on GD&T and Tolerance stackup analysis.
  • Creating designs for products based on customer requirements -Cooperation with internal and external partners/suppliers in order to build system components
  • Close collaboration with other worldwide customers.

Responsibilities :

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Qualification : BE / ME in ECE / EEE
Experience : 6 to 8 yrs
No of Position :

Requirements :

  • Candidate should have minimum 6 to 8 years experience in semi-conductor testing
  • Responsible for post silicon validation- Wafer and Package level
  • Strong working experience in Advantest/Verigy 93K or any ATE Tester.
  • Sound knowledge on Digital, Mixed signal and RF test methodologies
  • Experience in developing the test programs in ATE environment for Digital, mixed signal and RF devices.
  • First silicon verification and debug of Digital, Mixed Signal and RF devices using ATE tools and bench equipment.
  • Knowledge on Device Characterization and tester to tester correlation.
  • Knowledge on ATE hardware design (load board & probe card), PCB design tools and Signal Integrity analysis.
  • Knowledge on data extraction tool like Perl , Data power  and programming language C and C++.
  • Ability in Customer communication and interaction.
  • Knowledge on bench testing and high speed digital testing will be an added advantage.
  • Able to initiate and execute projects independently and should be a team player.

Responsibilities :

  • Work with design/DFT team to develop the detailed test procedure from device data sheet
  • Design and develop the required test hardware- Load board, bench board, Qualification board and probe card
  • Develop the ATE test program for device debug
  • First silicon verification and device bring up using ATE tools and bench equipment
  • Device characterization across temperature, voltage and process corners and validate the chip against the specification
  • Responsible for releasing  the Final production quality test program to the customer (both wafer final test program)
  • Interactions with the Design/DFT team through out the project execution
  • Interact with the customer on a daily basis and provide status update through e-mails and conference calls.
  • Experience in test program release procedure at production test house
  • Responsible from the beginning to the Final test/Wafer Test program release at customer site.

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Qualification : Any degree
Experience : 3 to 5 Yrs
No of Position :

Requirements :

  • Independently handling all types of visas, i.e Business Visas, Work Permits, Dependent Visas for Schengen countries, Asia and Asia Pacific Regions and also knowledge Australia, U.K, USA visas.
  • Schedule Interview with respective VFS / Consulates / and ensure timely submission of Visa Documents to respective VFS / Consulates / Travel Agents.
  • Coordinate with Travel Agents for visa fees and collection & DDs required for respective countries.
  • Co-coordinating with Travel Agents for issuing, insurance, tickets, hotel accommodation as required.
  • Creating daily reports of submission and collection dates
  • Co-ordinate with Travel desk operations with regard to internal customer’s requirements.
  • Interfacing with the otherdepartments within the company viz.  International Travel, Domestic Travels and Overseas HR, etc., at an operational level.
  • Analyzing problems and providing solutions in the best possible way
  • Able to work effectively as a team member
  • Well-disciplined and able to handle problems at any situation
  • Well versed in English
  • Interpersonal skill.
  • Quick learner
  • Efficient Management and Leadership quality
  • Enthusiasm to learn new things.

Responsibilities :

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Qualification : BE / ME in ECE / EEE
Experience : 3 to 5 yrs
No of Position :

Requirements :

  • High Speed digital and mixed signal board design
  • Schematic capturing, PCB Layout rules and approving placement/routing
  • Hardware debugging and support board bring up.
  • Knowledge of Signal integrity, power/thermal integrity, EMI handling
  • SOC/Processor based designs
  • Experience in high speed interfaces such as DDR2/3, PCI/PCIe, SATA, USB, Video interfaces etc.
  • Experience in DCDC converters and power management devices.
  • Knowledge of C and software flow.
  • Complete board Bringup and testing
  • Ability to work on multiple projects at given time
  • Experience in basic CPLD/RTL implementation (High desirable)
  • Strong communication skills and right attitude.
  • Effective customer facing skills

Responsibilities :

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Qualification : BE / ME in ECE / EEE
Experience : 5+ years
No of Position :

Requirements :

  • Testing program development on industry standard test platforms like Verigy 93000 and Teradyne test platform
  • Initial prototype test program development
  • Testing devices at wafer level and package level
  • Performing feasibility analysis and cross platform analysis
  • Test program Development and debugging
  • Production and yield analysis using tools like RAFT, Datapower and Spot Fire, Statistical analysis like Cpk, GRR and CGM
  • Understanding TINA or PSPICE platforms
  • Identifying and fixing any design errors or unforeseen issues in a timely manner
  • Participating in technical design and project management of testing methodologies on designs implemented for our customers
  • Working as an integral part of the sales process and offering technical feasibility feedback to the sales and executive management team
  • Reviewing and evaluating IC product testing requirements for customers
  • Providing package solutions within the packaging capability, package roadmap, process flow and design rules of the factory
  • Mentor fellow engineers in the field of Test and Product Engineering.

Responsibilities :

  • Bachelor Degree or foreign academic equivalent in Electronics and Communications Engineering Electrical & Electronics Engineering, Computer Engineering or related field plus 5 years of experience.
  • Required experience must include experience in Fastscan, DFT Compiler, Tetramax, Design Complier, VCS, NCSIM, LDV, Primetime, Cpk, GRR, Datapower and Spot Fire.

Click here to Apply for this Position

Qualification : BE/ME in ECE/EEE
Experience : 5+ years
No of Position : 3

Requirements :

  • Very good project execution and leadership skills

Responsibilities :

  • Responsible for post silicon validation at both Wafer and Package level.
  • Strong work experience in Advantest Verigy 93000, Teradyne Catalyst and NI STS ATE platforms is mandatory.
  • Experience in testing of MIPI RF Front End Switches is mandatory.
  • Develop test plan and test execution procedures to identify and mitigate the risk involved in the project.
  • Experience in developing turn-key test solutions in ATE environment for RF and mixed signal devices.
  • Experience in the design of ATE hardware (load board & probe card), PCB design tools and Signal Integrity analysis.
  • Develop test program using programming languages like C, C++, LabVIEW and TestStand.
  • First silicon verification and debug of RF, Mixed Signal (analog and digital) devices using ATE tools and bench equipment.
  • Validate and verify semiconductor IC using ATE solution by performing repeatability, correlation and temperature characterization.
  • Qualify the test solution by performing GRR, Spike check, Failure simulation and Test time optimization.
  • Knowledge on data extraction tools like Perl, Data power, Data conductor etc.
  • Excellent communication skills, and work with sales and business development of the company to be the engineering frontend for potential customers.

Click here to Apply for this Position

Qualification : BE - ECE / EEE
Experience : 3 to 5 Years
No of Position : -

Requirements :

  • • Candidate should have minimum 3 to 5 years’ experience in semi-conductor testing • Responsible for post silicon validation- Wafer and Package level • Strong working experience in Advantest/Verigy 93K or any ATE Tester. • Sound knowledge on Digital, Mixed signal test methodologies • Experience in developing the test programs in ATE environment for Digital, mixed signal devices. • First silicon verification and debug of Digital, Mixed Signal devices using ATE tools and bench equipment. • Knowledge on Device Characterization and tester to tester correlation. • Knowledge on ATE hardware design (load board & probe card), PCB design tools and Signal Integrity analysis. • Knowledge on data extraction tool like Perl , Data power and programming language C and C++. • Ability in Customer communication and interaction. • Knowledge on bench testing and high speed digital testing will be an added advantage. • Able to initiate and execute projects independently and should be a team player. • Notice Period - 1 Month.

Responsibilities :

  • Testing the latest semiconductor technologies

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Qualification : -
Experience : -
No of Position : -

Requirements :

  • A candidate with min 3 Years of Experience in Silicon validation and Characterization (OR) min of 3 Yrs design experience in Electronics HW industry with motivation to take up career as Characterization Engineer
  • Strong Electrical engineering fundamentals and exposure on complete HW Development cycle – an added advantage Proven experience in understanding the Device Data Sheet and derive the test methodology based on the Test plan provided Hands-on experience in one or more of the following – highly desirable industry standard Hi-Speed interfaces such as DDR-2, DDR-3, SATA, USB 2.0, USB 3.0, Display Port, PCI-e
  • Proficiency with measurements and related Lab Equipments – is must
  • Exposure on FPGA Design tools such as Xilinx / Altera – a major plus
  • Knowledge on Programming concepts and ‘C’ language – preferred
  • Strong communication skill

Responsibilities :

  • Prepares test and diagnostic programs, designs test fixtures to perform the System Testing & delivery, developing and implementing test automation sequence
  • The job involves device level debug and bring up, co-ordination with team lead to meet the deliverable, Lab Characterization of the Device developed, Device programming / testing new device samples for customers, board debugging etc.

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Qualification : -
Experience : 5 -10 Yrs
No of Position : -

Requirements :

  • Skills Required:
  • SoC Specification to Architecture implementation
  • Good experience in RTL Integration, CDC, Lint, Spyglass, LEC, Synthesis.
  • Experience in one of these is mandatory

Responsibilities :

  • Primary skill - Ethernet, Wi-Fi, Wlan, Memory Controllers, Data Paths, DDR, PCIE.
  • Secondary skill - USB, Bluetooth.

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Qualification : -
Experience : 5 -10 Yrs
No of Position : -

Requirements :

  • Job Location : Singapore
  • Skills Required
  • Good exposure in Specman -e, SV/UVM, C based directed testing
  • Ability to define a TB architecture for large SoC's.
  • Experience in one of this is mandator

Responsibilities :

  • Ethernet, Wi-Fi, Bluetooth, USB, PCIE, Memory Controllers, Data Paths, DDR.
  • Added advantage – Candidates with the experience in Network on chip.

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Qualification : -
Experience : -
No of Position : -

Requirements :

  • Looking for suitable engineers with 5 to 10 years of experience along with degree in BE/ B Tech/ ME/ M Tech preferably in EEE/ECE/EI
  • SoC RTL Integration/ LEC/ Synthesis/ Static Timing Analysis.
  • Tools: Synopsys DC Compiler, Primetime/ Signal Integrity.

Responsibilities :

    -

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 2 - 10 yrs
No of Position : -

Requirements :

  • Job Description :
  • Current requirements include activities involving
  • Digital/mixed-signal optimal DFT architecture definition rationalizing across test time/cost, coverage, dppm and customer quality
  • Plan DFT activities for self and the team
  • DFT logic integration and verification
  • Achieve coverage metrics
  • DFT automation and methodology
  • GateLevel DFT verification

Responsibilities :

  • Pattern generation, verification and delivery
  • Post silicon bringup and production support

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 to 10 years
No of Position : -

Requirements :

  • Job Description
  • Experience in SOC/IP/Sub-System DFT.
  • Technical leader who can assimilate customer requirements and help device execution plan Responsible and accountable with pro-active communication skills and a proven track record Strong technical contributor
  • Work in a team environment
  • Able and willing to provide technical mentorship to team members.
  • Support periodic training session and knowledge sharing sessions.
  • Should be able to work across cultural/functional/geographic boundaries Experienced in of all the aspects relating to Scan/ATPG
  • Scan synthesis, coverage metrics by fault-models – stuck-at, delay & Bridging
  • Memory BIST
  • Test Mode STA
  • Test power estimation, Boundary Scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing
  • Expert in EDA tools

Responsibilities :

  • Strong debug skills and automation savvy.
  • Post-Silicon debug and support

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 2 to 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • Digital, Mixed-Signal SOC/IP/Sub-System DFT
  • Individual contributor
  • Be able to work in a team
  • Be able to work with little or no supervision
  • Seek technical support as required
  • Should have sound understanding of all the design for test requirements
  • Should be able to comprehend DFT architecture, architecture limitations, schedule, volume of the task(s).
  • Aware of all the aspects relating to Scan/ATPG
  • Scan synthesis, coverage metrics by fault-models – stuck-at, delay & Bridging,
  • Memory bist
  • Test power estimation, Bounday scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing,
  • Post-Silicon debug and support
  • Knowledge of test STA
  • Debug skills and Automation savvy.
  • Good understanding of Gate-Level simulations and its nuances
  • Translate tool generated patterns to ATE platform
  • Be able to help in silicon debug both on ATE and at system level

Responsibilities :

  • Working knowledge of ATPG tools – Tetramax/Fastscan/Encounter.
  • Working knowledge of any or all of the simulation tools/environment

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 - 10yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design Verification
  • Mentoring
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Should have sound understanding of all the verification requirements
  • Should be able to comprehend architecture, architecture limitations from DV perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM (and or DSP) architecture
  • Good understanding of mixed-signal building blocks and their verification
  • Understanding of power management and its implication on verification
  • Test plan creation capturing all the functional requirements
  • Create, debug and validate all the test possibilities
  • Create IP and SOC test benches
  • Coverage (code & test cases) metric based verification sign-off
  • Good understanding of Gate-Level simulations and its nuances
  • Translate test cases to ATE platform to validate functionality & timing
  • Be able to help in silicon debug both on ATE and at system level
  • Failing test cases
  • Test case marginalities
  • Timing characterization
  • Functional issues

Responsibilities :

  • Good knowledge of C, C++, verilog, SystemVerilog ,UVM
  • Good knowledge of any or all of the simulation tools/environments

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design Verification
  • Strong hands-on individual contributors.
  • Be able and willing to work in a team environment.
  • Be able to support periodic training session and knowledge sharing sessions.
  • Strong debug skills and Automation savvy.
  • Good understanding of ARM (and or DSP) architecture
  • Good understanding of mixed-signal building blocks and their verification
  • Understanding of power management and its implication on verification
  • Test plan creation capturing all the functional requirements
  • Create, debug and validate all the test possibilities
  • Create IP and SOC test benches
  • Coverage (code & test cases) metric based verification sign-off
  • Good understanding of Gate-Level simulations and its nuances
  • Translate test cases to ATE platform to validate functionality & timing Be able to help in silicon debug both on ATE and at system level
  • Failing test cases
  • Test case marginalities
  • Timing characterization
  • Functional issues

Responsibilities :

  • Good knowledge of verilog, SystemVerilog VMM/UVM/C CPF,UPF
  • Good knowledge of any of the simulation tools/environments

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 – 10 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical expert.
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues (manufacturability, power, signal integrity, scaling)
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks)
  • Experience in Low power and high performance design
  • Experience in designing for automotive industry
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture

Responsibilities :

  • Good understanding of mixed-signal building blocks
  • Understanding of power management and its implication on physical design
  • Expert in tools Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical engineer
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues (manufacturability, power, signal integrity, scaling) Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks)
  • Experience in Low power and high performance design
  • Experience in designing for automotive industry
  • Be independent and be role model to junior team members - technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Good understanding of ARM -A15/A9 (and or DSP) architecture
  • Good understanding of mixed-signal building blocks

Responsibilities :

  • Understanding of power management and its implication on physical design
  • Expert in any of the tool set - Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 - 10 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical expert.
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues Experienced in leading Hard-IP/HardMacro/SOC timing closure with deep technical knowledge in all
  • Stages of the design - functional and test mode, core and IO constraints development, synthesis, optimization, STA setup with associated automation, cross-talk noise/dealy, STA signoff.
  • Experience in Low power and high performance design
  • Experience in designing for automotive industry
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the design requirements
  • Should be able to comprehend architecture, architecture limitations from STA/Synthesis perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture

Responsibilities :

  • Good understanding of mixed-signal building blocks
  • Understanding of power management and its implication on synthesis/STA
  • Expert in tools – any vendor.

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical expert.
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure with good technical knowledge in all
  • Stages of the design - functional and test mode, core and IO constraints development, synthesis, optimization, STA setup with associated automation, cross-talk noise/dealy, STA signoff.
  • Exposure to Low power, high performance designs, designing for automotive industry
  • Should be able to lead by example and be a role model for junior members in the team
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the design requirements

Responsibilities :

  • Should be able to comprehend architecture, architecture limitations from STA/Synthesis perspective Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture Good understanding of mixed-signal building blocks
  • Understanding of power management and its implication on synthesis/STA

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 10 years
No of Position : -

Requirements :

  • Job Description:
  • Specification study, Verification Plan Development for Analog/Mixed Signal blocks
  • Block Modelling and Verification in Verilog-AMS
  • Chip Top level Functional Simulation
  • Sign-off against Checklist before Tape Out release

Responsibilities :

  • Desired Skills & Experience:
  • Prior Analog Verification Experience up to 4 Years
  • Analog Circuit Design knowledge and/or experience
  • Experience in Verilog-AMS/Verilog A/VHDL-AMS/Verilog/SV
  • Experience in using Cadence Schematic Editor, ADE in a hands-on manner
  • Mixed Signal Verification
  • Good communication skills
  • Analog Mixed-Signal layout and verification for different complex analog circuits in 45nm node or lesser.Knowledge of half cell Tool Experience like Cadence Virtuso ,Vxl and Virtuoso, Schematic Composer, verifications tools including Assura, Mentor/Synopsys Calibre /Hercules LVS, DRC, STarRC for extraction

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