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Careers

Positions Open @ Tessolve
Looking for a suitable opening in Tessolve? Here are the positions open currently.

Qualification : BE/ME in ECE/EEE
Experience : 5+ years
No of Position : 3

Requirements :

  • Very good project execution and leadership skills

Responsibilities :

  • Responsible for post silicon validation at both Wafer and Package level.
  • Strong work experience in Advantest Verigy 93000, Teradyne Catalyst and NI STS ATE platforms is mandatory.
  • Experience in testing of MIPI RF Front End Switches is mandatory.
  • Develop test plan and test execution procedures to identify and mitigate the risk involved in the project.
  • Experience in developing turn-key test solutions in ATE environment for RF and mixed signal devices.
  • Experience in the design of ATE hardware (load board & probe card), PCB design tools and Signal Integrity analysis.
  • Develop test program using programming languages like C, C++, LabVIEW and TestStand.
  • First silicon verification and debug of RF, Mixed Signal (analog and digital) devices using ATE tools and bench equipment.
  • Validate and verify semiconductor IC using ATE solution by performing repeatability, correlation and temperature characterization.
  • Qualify the test solution by performing GRR, Spike check, Failure simulation and Test time optimization.
  • Knowledge on data extraction tools like Perl, Data power, Data conductor etc.
  • Excellent communication skills, and work with sales and business development of the company to be the engineering frontend for potential customers.

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Qualification : BE - ECE / EEE
Experience : 3 to 5 Years
No of Position : -

Requirements :

  • • Candidate should have minimum 3 to 5 years’ experience in semi-conductor testing • Responsible for post silicon validation- Wafer and Package level • Strong working experience in Advantest/Verigy 93K or any ATE Tester. • Sound knowledge on Digital, Mixed signal test methodologies • Experience in developing the test programs in ATE environment for Digital, mixed signal devices. • First silicon verification and debug of Digital, Mixed Signal devices using ATE tools and bench equipment. • Knowledge on Device Characterization and tester to tester correlation. • Knowledge on ATE hardware design (load board & probe card), PCB design tools and Signal Integrity analysis. • Knowledge on data extraction tool like Perl , Data power and programming language C and C++. • Ability in Customer communication and interaction. • Knowledge on bench testing and high speed digital testing will be an added advantage. • Able to initiate and execute projects independently and should be a team player. • Notice Period - 1 Month.

Responsibilities :

  • Testing the latest semiconductor technologies

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Qualification : -
Experience : -
No of Position : -

Requirements :

  • A candidate with min 3 Years of Experience in Silicon validation and Characterization (OR) min of 3 Yrs design experience in Electronics HW industry with motivation to take up career as Characterization Engineer
  • Strong Electrical engineering fundamentals and exposure on complete HW Development cycle – an added advantage Proven experience in understanding the Device Data Sheet and derive the test methodology based on the Test plan provided Hands-on experience in one or more of the following – highly desirable industry standard Hi-Speed interfaces such as DDR-2, DDR-3, SATA, USB 2.0, USB 3.0, Display Port, PCI-e
  • Proficiency with measurements and related Lab Equipments – is must
  • Exposure on FPGA Design tools such as Xilinx / Altera – a major plus
  • Knowledge on Programming concepts and ‘C’ language – preferred
  • Strong communication skill

Responsibilities :

  • Prepares test and diagnostic programs, designs test fixtures to perform the System Testing & delivery, developing and implementing test automation sequence
  • The job involves device level debug and bring up, co-ordination with team lead to meet the deliverable, Lab Characterization of the Device developed, Device programming / testing new device samples for customers, board debugging etc.

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Qualification : -
Experience : 5 -10 Yrs
No of Position : -

Requirements :

  • Skills Required:
  • SoC Specification to Architecture implementation
  • Good experience in RTL Integration, CDC, Lint, Spyglass, LEC, Synthesis.
  • Experience in one of these is mandatory

Responsibilities :

  • Primary skill - Ethernet, Wi-Fi, Wlan, Memory Controllers, Data Paths, DDR, PCIE.
  • Secondary skill - USB, Bluetooth.

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Qualification : -
Experience : 5 -10 Yrs
No of Position : -

Requirements :

  • Job Location : Singapore
  • Skills Required
  • Good exposure in Specman -e, SV/UVM, C based directed testing
  • Ability to define a TB architecture for large SoC's.
  • Experience in one of this is mandator

Responsibilities :

  • Ethernet, Wi-Fi, Bluetooth, USB, PCIE, Memory Controllers, Data Paths, DDR.
  • Added advantage – Candidates with the experience in Network on chip.

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Qualification : -
Experience : -
No of Position : -

Requirements :

  • Looking for suitable engineers with 5 to 10 years of experience along with degree in BE/ B Tech/ ME/ M Tech preferably in EEE/ECE/EI
  • SoC RTL Integration/ LEC/ Synthesis/ Static Timing Analysis.
  • Tools: Synopsys DC Compiler, Primetime/ Signal Integrity.

Responsibilities :

  • -

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 2 - 10 yrs
No of Position : -

Requirements :

  • Job Description :
  • Current requirements include activities involving
  • Digital/mixed-signal optimal DFT architecture definition rationalizing across test time/cost, coverage, dppm and customer quality
  • Plan DFT activities for self and the team
  • DFT logic integration and verification
  • Achieve coverage metrics
  • DFT automation and methodology
  • GateLevel DFT verification

Responsibilities :

  • Pattern generation, verification and delivery
  • Post silicon bringup and production support

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 to 10 years
No of Position : -

Requirements :

  • Job Description
  • Experience in SOC/IP/Sub-System DFT.
  • Technical leader who can assimilate customer requirements and help device execution plan Responsible and accountable with pro-active communication skills and a proven track record Strong technical contributor
  • Work in a team environment
  • Able and willing to provide technical mentorship to team members.
  • Support periodic training session and knowledge sharing sessions.
  • Should be able to work across cultural/functional/geographic boundaries Experienced in of all the aspects relating to Scan/ATPG
  • Scan synthesis, coverage metrics by fault-models – stuck-at, delay & Bridging
  • Memory BIST
  • Test Mode STA
  • Test power estimation, Boundary Scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing
  • Expert in EDA tools

Responsibilities :

  • Strong debug skills and automation savvy.
  • Post-Silicon debug and support

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Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 2 to 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • Digital, Mixed-Signal SOC/IP/Sub-System DFT
  • Individual contributor
  • Be able to work in a team
  • Be able to work with little or no supervision
  • Seek technical support as required
  • Should have sound understanding of all the design for test requirements
  • Should be able to comprehend DFT architecture, architecture limitations, schedule, volume of the task(s).
  • Aware of all the aspects relating to Scan/ATPG
  • Scan synthesis, coverage metrics by fault-models – stuck-at, delay & Bridging,
  • Memory bist
  • Test power estimation, Bounday scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing,
  • Post-Silicon debug and support
  • Knowledge of test STA
  • Debug skills and Automation savvy.
  • Good understanding of Gate-Level simulations and its nuances
  • Translate tool generated patterns to ATE platform
  • Be able to help in silicon debug both on ATE and at system level

Responsibilities :

  • Working knowledge of ATPG tools – Tetramax/Fastscan/Encounter.
  • Working knowledge of any or all of the simulation tools/environment

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 - 10yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design Verification
  • Mentoring
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Should have sound understanding of all the verification requirements
  • Should be able to comprehend architecture, architecture limitations from DV perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM (and or DSP) architecture
  • Good understanding of mixed-signal building blocks and their verification
  • Understanding of power management and its implication on verification
  • Test plan creation capturing all the functional requirements
  • Create, debug and validate all the test possibilities
  • Create IP and SOC test benches
  • Coverage (code & test cases) metric based verification sign-off
  • Good understanding of Gate-Level simulations and its nuances
  • Translate test cases to ATE platform to validate functionality & timing
  • Be able to help in silicon debug both on ATE and at system level
  • Failing test cases
  • Test case marginalities
  • Timing characterization
  • Functional issues

Responsibilities :

  • Good knowledge of C, C++, verilog, SystemVerilog ,UVM
  • Good knowledge of any or all of the simulation tools/environments

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design Verification
  • Strong hands-on individual contributors.
  • Be able and willing to work in a team environment.
  • Be able to support periodic training session and knowledge sharing sessions.
  • Strong debug skills and Automation savvy.
  • Good understanding of ARM (and or DSP) architecture
  • Good understanding of mixed-signal building blocks and their verification
  • Understanding of power management and its implication on verification
  • Test plan creation capturing all the functional requirements
  • Create, debug and validate all the test possibilities
  • Create IP and SOC test benches
  • Coverage (code & test cases) metric based verification sign-off
  • Good understanding of Gate-Level simulations and its nuances
  • Translate test cases to ATE platform to validate functionality & timing Be able to help in silicon debug both on ATE and at system level
  • Failing test cases
  • Test case marginalities
  • Timing characterization
  • Functional issues

Responsibilities :

  • Good knowledge of verilog, SystemVerilog VMM/UVM/C CPF,UPF
  • Good knowledge of any of the simulation tools/environments

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 – 10 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical expert.
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues (manufacturability, power, signal integrity, scaling)
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks)
  • Experience in Low power and high performance design
  • Experience in designing for automotive industry
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture

Responsibilities :

  • Good understanding of mixed-signal building blocks
  • Understanding of power management and its implication on physical design
  • Expert in tools Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical engineer
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues (manufacturability, power, signal integrity, scaling) Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks)
  • Experience in Low power and high performance design
  • Experience in designing for automotive industry
  • Be independent and be role model to junior team members - technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Good understanding of ARM -A15/A9 (and or DSP) architecture
  • Good understanding of mixed-signal building blocks

Responsibilities :

  • Understanding of power management and its implication on physical design
  • Expert in any of the tool set - Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 - 10 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical expert.
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues Experienced in leading Hard-IP/HardMacro/SOC timing closure with deep technical knowledge in all
  • Stages of the design - functional and test mode, core and IO constraints development, synthesis, optimization, STA setup with associated automation, cross-talk noise/dealy, STA signoff.
  • Experience in Low power and high performance design
  • Experience in designing for automotive industry
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the design requirements
  • Should be able to comprehend architecture, architecture limitations from STA/Synthesis perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture

Responsibilities :

  • Good understanding of mixed-signal building blocks
  • Understanding of power management and its implication on synthesis/STA
  • Expert in tools – any vendor.

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical expert.
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure with good technical knowledge in all
  • Stages of the design - functional and test mode, core and IO constraints development, synthesis, optimization, STA setup with associated automation, cross-talk noise/dealy, STA signoff.
  • Exposure to Low power, high performance designs, designing for automotive industry
  • Should be able to lead by example and be a role model for junior members in the team
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the design requirements

Responsibilities :

  • Should be able to comprehend architecture, architecture limitations from STA/Synthesis perspective Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture Good understanding of mixed-signal building blocks
  • Understanding of power management and its implication on synthesis/STA

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 10 years
No of Position : -

Requirements :

  • Job Description:
  • Specification study, Verification Plan Development for Analog/Mixed Signal blocks
  • Block Modelling and Verification in Verilog-AMS
  • Chip Top level Functional Simulation
  • Sign-off against Checklist before Tape Out release

Responsibilities :

  • Desired Skills & Experience:
  • Prior Analog Verification Experience up to 4 Years
  • Analog Circuit Design knowledge and/or experience
  • Experience in Verilog-AMS/Verilog A/VHDL-AMS/Verilog/SV
  • Experience in using Cadence Schematic Editor, ADE in a hands-on manner
  • Mixed Signal Verification
  • Good communication skills
  • Analog Mixed-Signal layout and verification for different complex analog circuits in 45nm node or lesser.Knowledge of half cell Tool Experience like Cadence Virtuso ,Vxl and Virtuoso, Schematic Composer, verifications tools including Assura, Mentor/Synopsys Calibre /Hercules LVS, DRC, STarRC for extraction

Click here to Apply for this Position

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