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Positions Open @ Tessolve
Looking for a suitable opening in Tessolve? Here are the positions open currently.

Venue details for Walk-in (Online Test) for the position of Test Engineers on 03-Jun-2017.

ICRIS Pratheeksha,
Srinidhi complex 11/3,
2nd floor & cross Hosur main road Adugodi,
Bangalore
Landmark : Above BESCOM Office
Date of online test : 3rd June 2017.

Qualification : BE / B Tech in Electronics and Communications / Electrical & Electronics Engineering
Experience : 1 - 3 years
No of Position :

Requirements :

  • Hardware Design / Test : Good understanding of analog / digital Hardware circuit design, Assist PCB design, Hands on experience with Test equipment like oscilloscope, signal generator / analyzer, pattern generator etc.
  • Embedded design: Experience with FPGA, Microcontroller based application development, Verilog / VHDL, Embeded C development
  • High Speed: Test experience with High-Speed SERDES (USB, DDR, SATA, PCIe, MIPI PHY, HDMI etc)
  • Mixed Signal: Test Experience with Mixed-signal blocks like ADC/ DAC and PLL blocks
  • RF: Experience in designing and testing of RF circuits
  • Power Electronics: Power management systems design and testing of DC-DC Converters like Buck/boost, LDO regulators etc.

Responsibilities :

  • Developing ATE / Bench test solution for semiconductor IC’s in different domains as Power management / Digital / Mixed signal or RF.
  • Be a primary contact to interact with customer / vendors (design / support teams)
  • Work with design/DFT team to develop the detailed test procedure from device data sheet
  • Develop and lead the hardware design activity (Probe cards / Final test load boards), develop schematics, provide placement / layout guidelines to PCB design engineer
  • Post silicon verification and device bring up using ATE tools. Leading ATE’s from Teradyne, Advantest etc (Uflex, 93K etc)
  • ATE software development as per test procedure document (C, C++, Perl, VB etc)
  • Responsible for releasing the Final Test / Wafer Sort test programs to production site

Click here to Apply for this Position

Qualification : BE / B Tech in Electronics and Communications / Electrical & Electronics Engineering with an aggregate of 65 % & above
Experience : Only 2016 & 2017 Passed out candidates
No of Position :

Requirements :

  • Should have good analytical and problem solving skills
  • Ability to express new ideas
  • Interpersonal skills and Communication skills

Responsibilities :

  • ATE based testing (Verigy/Advantest, Teradyne/Eagle, any other testers including custom made testers)
  • Bench testing – TestStand, LabView tools
  • Hardware design engineer - Board design (Digital, Mixed signal, RF)
  • Application engineer in ATE
  • FPGA testing using JTAG / BoundaryScan
  • System level testing
  • Embedded testing & debugging

Click here to Apply for this Position

Qualification : BE - ECE / EEE
Experience : 2 - 5 Years
No of Position : -

Requirements :

  • 2 - 5 Years of experience

Responsibilities :

  • • Supporting RF bench test system development • Test Tune and debug RFIC hardware • Manual Testing knowledge of Transmitters, Receivers, Synthesizers • Matching on RF test hardware using Smith charts • Working with Bench Test Engineers, IC Design Engineers, Systems Engineers, and Product Engineers • Knowledge on Lab view and data analysis • Knowledge about various transceiver architecture and cascaded power budget analysis • Experience on ATE is an added advantage • Good communication and interpersonal skills

Click here to Apply for this Position

Qualification : BE - ECE / EEE
Experience : 3 to 5 Years
No of Position : -

Requirements :

  • • Candidate should have minimum 3 to 5 years’ experience in semi-conductor testing • Responsible for post silicon validation- Wafer and Package level • Strong working experience in Advantest/Verigy 93K or any ATE Tester. • Sound knowledge on Digital, Mixed signal test methodologies • Experience in developing the test programs in ATE environment for Digital, mixed signal devices. • First silicon verification and debug of Digital, Mixed Signal devices using ATE tools and bench equipment. • Knowledge on Device Characterization and tester to tester correlation. • Knowledge on ATE hardware design (load board & probe card), PCB design tools and Signal Integrity analysis. • Knowledge on data extraction tool like Perl , Data power and programming language C and C++. • Ability in Customer communication and interaction. • Knowledge on bench testing and high speed digital testing will be an added advantage. • Able to initiate and execute projects independently and should be a team player. • Notice Period - 1 Month.

Responsibilities :

  • Testing the latest semiconductor technologies

Click here to Apply for this Position

Qualification : -
Experience : -
No of Position : -

Requirements :

  • A self-motivated BE / B Tech candidate & 7 to 10 Years of Experience in Electronics HW
  • Strong Electrical engineering fundamentals and exposure on complete HW Development cycle from conceptualization to realization
  • Proven experience in designing Hi-Speed Mixed / Digital Boards based on Device Data Sheet and working experience with EDA tools such as Cadence Allegro, OrCAD Schematic Capture etc.,
  • Very Good experience in (MIPS / ARM / Power PC) Processor based system designs & good HW Debugging skill
  • Hands-on experience in one or more of the industry standard Hi-Speed interfaces such as DDR-2, DDR-3, SATA, USB 2.0, USB 3.0, Display Port, PCI-e, GB-Ethernet (10BASE-T / 100BASE-TX/1000BASE-T) etc.,
  • Proficiency with Hi-Speed measurements and related Lab Equipments Good mentoring, Communication Skill and Team work
  • Exposure on FPGA Design tools such as Xilinx / Altera – a major plus
  • Knowledge on Programming concepts and ‘C’ language

Responsibilities :

  • Responsible for designing, developing, and implementing cost-effective systems with hi-speed interface standards
  • Prepares test and diagnostic programs, designs test fixtures to perform the System Testing & delivery, Mentoring Junior Engineers and identify
  • Training Requirements for the team members The job involves device level debug and bring up, co-ordination with Device vendors, Lab Characterization of the System developed, Device programming / testing new device samples for customers, board debugging etc.
  • Candidate should be able to come up with effort estimate on complex system design projects and identify right resources in-house for the activities involved & guide the team to achieve the goal resulting in success of the organization

Click here to Apply for this Position

Qualification : -
Experience : -
No of Position : -

Requirements :

  • A candidate with 3 to 5 Years of Experience in Electronics HW with processor based design experience & strong debug skill
  • Strong Electrical engineering fundamentals and exposure on complete HW Development cycle
  • Proven experience in designing HW Analog / Digital Boards based on Device Data Sheet and working experience with EDA tools such as Cadence
  • Allegro, OrCAD Schematic Capture etc.,
  • Hands-on experience in one or more of the industry standard Hi-Speed interfaces such as DDR-2, DDR-3, SATA, USB 2.0, USB 3.0, Display Port, PCI-e
  • Proficiency with measurements and related Lab Equipments
  • Exposure on FPGA Design tools such as Xilinx / Altera – a major plus
  • Knowledge on Programming concepts and ‘C’ language
  • Strong communication skill

Responsibilities :

  • Get involved in designing, developing, and implementing cost-effective processor based systems
  • Prepares test and diagnostic programs, designs test fixtures to perform the System Testing & delivery
  • The job involves device level debug and bring up, co-ordination with Device vendors, Lab Characterization of the System developed, Device programming / testing new device samples for customers, board debugging etc.

Click here to Apply for this Position

Qualification : BE/B.Tech in EEE/ECE
Experience : -
No of Position : -

Requirements :

  • Play a critical role in developing ATE test hardware and software solutions.
  • Able to independently handle the projects starting from Schematic design, FPGA control logic development, BOM selection, Test Program
  • Development, Debug and proto release, System Level Testing, FPGA Testing, Bench Testing, Board design.
  • Responsible for a complete Turn Key Solution development on ATEs to test different Integrated circuits.
  • Write the test development spec for particular product from design spec or datasheet.
  • Design and document the test hardware - probe cards, DUT load boards, load boards etc.
  • Develop test programs and document Product Test Specification for products assigned on target ATE platform.
  • Conversion of solutions across test platforms and test time reduction to improve the productivity.
  • Performing bench-to-ATE correlation – reproducibility, repeatability by working with Product Engineers.
  • Release of the Test Solution to production.
  • Must be hands on and ready to take up any challenging project. Strong teamwork and communication skills.
  • Work with a team of Engineers and bring them up to speed on developing turnkey solutions.

Responsibilities :

  • Expertise in testing the latest semiconductor technologies i.e. MEMS devices, Microcontrollers, etc. will be an added advantage.
  • Status : Open

Click here to Apply for this Position

Qualification : BE (CSE/IT) / MCA
Experience : 3 to 7 years
No of Position : -

Requirements :

  • Job Location : Visakhapatnam / Bangalore
  • As a Software Engineer - you will contribute to the analysis, design & development of features, creation of work plans. You must be able to understand requirements, existing features, design and architect solutions. You will have opportunity to learn and implement both existing and new technologies, especially Digia Qt and C++/C# on Windows platform.

Responsibilities :

  • Skills & Experience:
  • Hands-on experience on Digia Qt.
  • Hands-on experience on C++ or C#.
  • Should have development experience on Windows Application and DLL.
  • Ability to design and develop independently follow development processes, reviews and integration to handle releases.
  • Strong ability to understand existing code and create quality code from design models/documents.
  • Good understanding of object oriented design and knowledge of product life cycles.
  • Experience with any ATE test systems highly desirable.
  • Additional Skills:
  • Programming knowledge on PERL, PASCAL, VB & MATLAB
  • ATE – Pattern Conversion tool development experience.
  • Digital logic basics.
  • Status : Open

Click here to Apply for this Position

Qualification : -
Experience : -
No of Position : -

Requirements :

  • A self-motivated Senior Software Engineer (5 to 7 Years of Experience in Embedded SW Development)
  • Strong C / C++ programming skills and hands-on development experience using Linux/ VxWorks
  • RTOS preferably VxWorks / Linux Kernel development with extensive experience in ARM/x86/PPC Architecture.
  • Device driver development, Driver adaption, porting, enhancing & fine tuning the Kernel.
  • Development knowledge on BSP is must.
  • Knowledge on Boot architecture U-Boot & GRUB.
  • Knowledge on Kernel debugging tools like JTAG/T32/GDB.
  • Experience in developing embedded application SW in any RTOS (VxWorks) / LINUX Kernel space & user space.
  • Familiar with every stage in SW Development cycle
  • Good mentoring, Communication Skill and Team work
  • Strong in communication and customer interaction with right attitude
  • Knowledge on Programming concepts and ‘C’ language
  • Should have excellent team build capabilities / Management

Responsibilities :

  • Understand complete requirements from customer and translate them it into SW implementable modules for the HW / OS platforms
  • Responsible for designing, developing, and implementing right embedded SW systems and track the SW Development schedule
  • To co-ordinate with Program Managers / Customers on-site and participate in discussions related to new projects
  • The job involves device level debug and bring up in co-ordination with HW Team and Designers on-site
  • This position calls for 30% of travelling abroad

Click here to Apply for this Position

Qualification : -
Experience : -
No of Position : -

Requirements :

  • Proven experience in deriving test plan based on chip data sheet, test board HW design, test automation with min of 6 to 7 Years of Experience
  • Proven experience in bench test of High Speed Digital IP Modules / Controller based SOCs with popular high speed interface standards such as DDR2/DDR3/SATA/MIPI-MPHY/MIPI-DPHY/CSI/USB2.0/USB3.0/PCI-e etc.,
  • Working experience in bring up of Complex Boards and preparation of Bench Test Setup with high end equipment
  • Strong Electrical engineering fundamentals with ability to identify suitable test equipment & test methodology requirement to perform Post Si Validation and Characterization
  • Experience in using / controlling basic lab equipments like Oscilloscopes, Spectrum analyzers, clock and timing sources, signal generators etc
  • Exposure on Lab Automation tools (LabVIEW) / scripting languages – highly desirable
  • Ability to write SW macros / Test script to program SOC module – a major plus
  • Exposure on FPGA Design Tools such as Xilinx / Altera – added advantage but not desired
  • Good mentoring, Communication Skill and Team work
  • Ability to lead a team of 3 to 4 engineers and represent the team at customer site
  • Coordinate with designers on-site to ensure meet characterization schedule

Responsibilities :

  • Responsible for designing, developing, and implementing cost-effective methods of testing and troubleshooting systems and equipment
  • Prepares test and diagnostic programs, designs test fixtures & carry out complete Electrical Characterization and Debug of the device
  • Mentoring Junior Engineers and identify Training Requirements for the team members
  • The job involves device level debug and bring up, co-ordination with Equipment vendors, Lab Characterization of the device developed, Device programming / testing new device samples for customers etc.
  • To get involved in understanding new requirements from Design Team, participate in the Technical discussions and prepare test, debug and compliance reports as per customer requirement

Click here to Apply for this Position

Qualification : -
Experience : -
No of Position : -

Requirements :

  • A candidate with min 3 Years of Experience in Silicon validation and Characterization (OR) min of 3 Yrs design experience in Electronics HW industry with motivation to take up career as Characterization Engineer
  • Strong Electrical engineering fundamentals and exposure on complete HW Development cycle – an added advantage Proven experience in understanding the Device Data Sheet and derive the test methodology based on the Test plan provided Hands-on experience in one or more of the following – highly desirable industry standard Hi-Speed interfaces such as DDR-2, DDR-3, SATA, USB 2.0, USB 3.0, Display Port, PCI-e
  • Proficiency with measurements and related Lab Equipments – is must
  • Exposure on FPGA Design tools such as Xilinx / Altera – a major plus
  • Knowledge on Programming concepts and ‘C’ language – preferred
  • Strong communication skill

Responsibilities :

  • Prepares test and diagnostic programs, designs test fixtures to perform the System Testing & delivery, developing and implementing test automation sequence
  • The job involves device level debug and bring up, co-ordination with team lead to meet the deliverable, Lab Characterization of the Device developed, Device programming / testing new device samples for customers, board debugging etc.

Click here to Apply for this Position

Qualification : -
Experience : 3- 4Years
No of Position : -

Requirements :

  • Job Location : Bangalore
  • A self-motivated BE / B Tech candidate with experience in FPGA FW implementation using industry popular tools such as Altera / Xilinx.
  • Strong Electrical engineering fundamentals and exposure on complete FPGA Code Development cycle from conceptualization to realization
  • Proven experience in designing VHDL for highly complex systems with FPGA implementation
  • Good experience in (MIPS / ARM / Power PC) Processor based systems & good Debugging skill
  • Hands-on experience in one or more of the industry standard Hi-Speed interfaces such as DDR-2, DDR-3, SATA, USB 2.0, USB 3.0, Display Port, PCI-e, GB-Ethernet (10BASE-T / 100BASE-TX/1000BASE-T) etc.,
  • Proficiency with selecting right target device for the given application
  • Good mentoring, Communication Skill and Team work
  • Knowledge on Programming concepts and ‘C’ language – a plus (not desired)

Responsibilities :

  • Responsible for designing, developing, and implementing cost-effective complex systems using FPGAs with hi-speed interface standards Should be able to visualize top level requirements in detail and guide the team towards achieving the goal of implementing the architecture successfully
  • Identifies test and diagnostic programs required at various stages of the module integration in targeted FPGA
  • The job involves debug at VHDL / Gate level and bring up, co-ordination with Device vendors, Device programming /targeting new device samples for new designs etc.
  • Candidate should be able to come up with effort estimate on complex system design projects and identify right resources in-house for the activities involved & guide the team to achieve the goal resulting in success of the organization

Click here to Apply for this Position

Qualification : -
Experience : 5 -10 Yrs
No of Position : -

Requirements :

  • Skills Required:
  • SoC Specification to Architecture implementation
  • Good experience in RTL Integration, CDC, Lint, Spyglass, LEC, Synthesis.
  • Experience in one of these is mandatory

Responsibilities :

  • Primary skill - Ethernet, Wi-Fi, Wlan, Memory Controllers, Data Paths, DDR, PCIE.
  • Secondary skill - USB, Bluetooth.

Click here to Apply for this Position

Qualification : -
Experience : 5 -10 Yrs
No of Position : -

Requirements :

  • Job Location : Singapore
  • Skills Required
  • Good exposure in Specman -e, SV/UVM, C based directed testing
  • Ability to define a TB architecture for large SoC's.
  • Experience in one of this is mandator

Responsibilities :

  • Ethernet, Wi-Fi, Bluetooth, USB, PCIE, Memory Controllers, Data Paths, DDR.
  • Added advantage – Candidates with the experience in Network on chip.

Click here to Apply for this Position

Qualification : -
Experience : -
No of Position : -

Requirements :

  • Looking for suitable engineers with 5 to 10 years of experience along with degree in BE/ B Tech/ ME/ M Tech preferably in EEE/ECE/EI
  • SoC RTL Integration/ LEC/ Synthesis/ Static Timing Analysis.
  • Tools: Synopsys DC Compiler, Primetime/ Signal Integrity.

Responsibilities :

  • -

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 2 - 10 yrs
No of Position : -

Requirements :

  • Job Description :
  • Current requirements include activities involving
  • Digital/mixed-signal optimal DFT architecture definition rationalizing across test time/cost, coverage, dppm and customer quality
  • Plan DFT activities for self and the team
  • DFT logic integration and verification
  • Achieve coverage metrics
  • DFT automation and methodology
  • GateLevel DFT verification

Responsibilities :

  • Pattern generation, verification and delivery
  • Post silicon bringup and production support

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 to 10 years
No of Position : -

Requirements :

  • Job Description
  • Experience in SOC/IP/Sub-System DFT.
  • Technical leader who can assimilate customer requirements and help device execution plan Responsible and accountable with pro-active communication skills and a proven track record Strong technical contributor
  • Work in a team environment
  • Able and willing to provide technical mentorship to team members.
  • Support periodic training session and knowledge sharing sessions.
  • Should be able to work across cultural/functional/geographic boundaries Experienced in of all the aspects relating to Scan/ATPG
  • Scan synthesis, coverage metrics by fault-models – stuck-at, delay & Bridging
  • Memory BIST
  • Test Mode STA
  • Test power estimation, Boundary Scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing
  • Expert in EDA tools

Responsibilities :

  • Strong debug skills and automation savvy.
  • Post-Silicon debug and support

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 2 to 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • Digital, Mixed-Signal SOC/IP/Sub-System DFT
  • Individual contributor
  • Be able to work in a team
  • Be able to work with little or no supervision
  • Seek technical support as required
  • Should have sound understanding of all the design for test requirements
  • Should be able to comprehend DFT architecture, architecture limitations, schedule, volume of the task(s).
  • Aware of all the aspects relating to Scan/ATPG
  • Scan synthesis, coverage metrics by fault-models – stuck-at, delay & Bridging,
  • Memory bist
  • Test power estimation, Bounday scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing,
  • Post-Silicon debug and support
  • Knowledge of test STA
  • Debug skills and Automation savvy.
  • Good understanding of Gate-Level simulations and its nuances
  • Translate tool generated patterns to ATE platform
  • Be able to help in silicon debug both on ATE and at system level

Responsibilities :

  • Working knowledge of ATPG tools – Tetramax/Fastscan/Encounter.
  • Working knowledge of any or all of the simulation tools/environment

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 - 10yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design Verification
  • Mentoring
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Should have sound understanding of all the verification requirements
  • Should be able to comprehend architecture, architecture limitations from DV perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM (and or DSP) architecture
  • Good understanding of mixed-signal building blocks and their verification
  • Understanding of power management and its implication on verification
  • Test plan creation capturing all the functional requirements
  • Create, debug and validate all the test possibilities
  • Create IP and SOC test benches
  • Coverage (code & test cases) metric based verification sign-off
  • Good understanding of Gate-Level simulations and its nuances
  • Translate test cases to ATE platform to validate functionality & timing
  • Be able to help in silicon debug both on ATE and at system level
  • Failing test cases
  • Test case marginalities
  • Timing characterization
  • Functional issues

Responsibilities :

  • Good knowledge of C, C++, verilog, SystemVerilog ,UVM
  • Good knowledge of any or all of the simulation tools/environments

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design Verification
  • Strong hands-on individual contributors.
  • Be able and willing to work in a team environment.
  • Be able to support periodic training session and knowledge sharing sessions.
  • Strong debug skills and Automation savvy.
  • Good understanding of ARM (and or DSP) architecture
  • Good understanding of mixed-signal building blocks and their verification
  • Understanding of power management and its implication on verification
  • Test plan creation capturing all the functional requirements
  • Create, debug and validate all the test possibilities
  • Create IP and SOC test benches
  • Coverage (code & test cases) metric based verification sign-off
  • Good understanding of Gate-Level simulations and its nuances
  • Translate test cases to ATE platform to validate functionality & timing Be able to help in silicon debug both on ATE and at system level
  • Failing test cases
  • Test case marginalities
  • Timing characterization
  • Functional issues

Responsibilities :

  • Good knowledge of verilog, SystemVerilog VMM/UVM/C CPF,UPF
  • Good knowledge of any of the simulation tools/environments

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 – 10 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical expert.
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues (manufacturability, power, signal integrity, scaling)
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks)
  • Experience in Low power and high performance design
  • Experience in designing for automotive industry
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture

Responsibilities :

  • Good understanding of mixed-signal building blocks
  • Understanding of power management and its implication on physical design
  • Expert in tools Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical engineer
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues (manufacturability, power, signal integrity, scaling) Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks)
  • Experience in Low power and high performance design
  • Experience in designing for automotive industry
  • Be independent and be role model to junior team members - technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Good understanding of ARM -A15/A9 (and or DSP) architecture
  • Good understanding of mixed-signal building blocks

Responsibilities :

  • Understanding of power management and its implication on physical design
  • Expert in any of the tool set - Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 8 - 10 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical expert.
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues Experienced in leading Hard-IP/HardMacro/SOC timing closure with deep technical knowledge in all
  • Stages of the design - functional and test mode, core and IO constraints development, synthesis, optimization, STA setup with associated automation, cross-talk noise/dealy, STA signoff.
  • Experience in Low power and high performance design
  • Experience in designing for automotive industry
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the design requirements
  • Should be able to comprehend architecture, architecture limitations from STA/Synthesis perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture

Responsibilities :

  • Good understanding of mixed-signal building blocks
  • Understanding of power management and its implication on synthesis/STA
  • Expert in tools – any vendor.

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 8 Yrs
No of Position : -

Requirements :

  • Job Description:
  • SOC/IP/Sub-System Design
  • Must be hands-on technical expert.
  • Strong written and oral communication skills
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure with good technical knowledge in all
  • Stages of the design - functional and test mode, core and IO constraints development, synthesis, optimization, STA setup with associated automation, cross-talk noise/dealy, STA signoff.
  • Exposure to Low power, high performance designs, designing for automotive industry
  • Should be able to lead by example and be a role model for junior members in the team
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the design requirements

Responsibilities :

  • Should be able to comprehend architecture, architecture limitations from STA/Synthesis perspective Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture Good understanding of mixed-signal building blocks
  • Understanding of power management and its implication on synthesis/STA

Click here to Apply for this Position

Qualification : BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS
Experience : 5 - 10 years
No of Position : -

Requirements :

  • Job Description:
  • Specification study, Verification Plan Development for Analog/Mixed Signal blocks
  • Block Modelling and Verification in Verilog-AMS
  • Chip Top level Functional Simulation
  • Sign-off against Checklist before Tape Out release

Responsibilities :

  • Desired Skills & Experience:
  • Prior Analog Verification Experience up to 4 Years
  • Analog Circuit Design knowledge and/or experience
  • Experience in Verilog-AMS/Verilog A/VHDL-AMS/Verilog/SV
  • Experience in using Cadence Schematic Editor, ADE in a hands-on manner
  • Mixed Signal Verification
  • Good communication skills
  • Analog Mixed-Signal layout and verification for different complex analog circuits in 45nm node or lesser.Knowledge of half cell Tool Experience like Cadence Virtuso ,Vxl and Virtuoso, Schematic Composer, verifications tools including Assura, Mentor/Synopsys Calibre /Hercules LVS, DRC, STarRC for extraction

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