Tessolve has expertise in RTL front end design targeting to FPGA and ASIC designs. Engineers are well trained and have expertise to design RTL sub blocks and integration from specification to architecture and coding involving block level functional test. Engineers are trained to integrate the third party IP’s with minimal interactions with the IP owners and parallel support verification team with debug support and coverage score improvement.
- Expertise in integration activity of SOC for functional and test chips.
- Expertise in handling multi clock domain and multi voltage domain SOC’s.
- Implementing SCAN aware ports during integration.
- Integration with register set generation including JTAG register features for CSR.
- Glue logic development support including bridge development for AHB/AXI and custom blocks.
- Manual integration along with client custom script based integration environment expertise.
- Linting checks for integrated entire SOC level.
- CDC checks for complete coverage of SOC.
- Functionality connectivity checks and correcting as per the feedback from DFT and PD teams.
Logical Equivalence Check (LEC):
- Expertise in SOC level post synthesis equivalence checks.
- Synthesizing designs at block level in topographical mode with high quality QoR.
- UPF base synthesis.
- Analyzing issues during synthesis and fixing them to improve QoR.
- Developing and validating constraints for block and top level.
- Coordinating with DFT team for scan insertion.
- Updating constraints based on STA feedback.
- Formal verification on RTL and synthesis net list.
- Validating constraints and ETM generation for blocks.
- Analyzing timing reports and fixing issues,
- Updating constraints as per analysis.