Design verification (DV) is a rapidly changing field and highly involved in the design process and requires developing and deploying new verification methodologies. Verification is a highly essential part of the design cycle in ASIC flow. Verification domain is evolving day-by-day as EDA groups work together to bring out the best methodologies to reduce the debug time as Verification consumes majority of the time in the design cycle which cannot be evaded. Our engineers work very closely with our clients facing various challenges in IP level to SOC level by providing customized and flexible solutions.
- Developing test plans for the complex designs, designing and developing verification environments. Applying these to verify designs until functional coverage, code coverage and performance goals are met.
- Instruction driven verification (tests coded in C or assembly language), Assertions, simulation, HW-SW co-verification, constraint\HVL-based verification (System Verilog, VERA/e-Specman, UVM & OVM), SystemC & FSM verification.
- Formal Design Verification (Static Property Checking, Jasper, IFV & Model Checking).
- Work with the architects, designers and SW engineers of these designs to plan and execute verification and validation of these designs for integration into SoCs for mobile applications.
- Low-Power Design Verification (UPF based Power Aware RTL and Gate Level Simulations).
- Gate Level Unit delay and SDF annotated timing simulations.
- Verification, Design & Automation (EDA tools, Simulation Acceleration, Hardware Emulation: EVE, Cadence Palladium, Mentor Veloce, Synopsys HAPS, FPGA/ASIC-based emulator).
- At SoC level, generate cyclic functional vectors for Silicon testing/characterization and validating them in RTL and in Zero-delay/SDF annotated Gate Level Simulation environment.
- Aid Post-Silicon Validation teams in Silicon bring up and debug.
- Verilog or VHDL
- System Verilog
- Cadence Ncsim
- Synopsys VCS
- Mentor Graphics Modelsim
- Video codec h.264/MPEG/VC1/HEVC.
- Camera ISP, JPEG encoder/decoder, MIPI-CSI.
- CPU ARM, AMBA, AHB, AXI, Peripherals, Clock and Security and cache coherent bus protocols.
- Graphics – OpenGL/CL, DX-9/10/11.
- Next generation processors for Smart phones and Test chips.
- High Speed I/O s like PCIe, USB 3.0, DDR.